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Why do I get a pole-zero doublet when I do the CMFB stability test?

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meghna

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Hi,
I am designing a CMFB circuit for a folded cascode amplifier in Spectre. When I do the CMFB stability test, I get one pole-zero doublet at some intermediate node. (that zero is left half plane zero) My feeling is that diode connected transistor in CMFB circuit is giving the doublet. But I am not able to understand it exactly. Can someone please help!

Thanks
Meghna
 

pole-zero doublet

I think you are correct. The pole-zero doublet could be because of the diode connected MOSFET in the loop. In case this doublet is much beyong the loop GBW, there is no reason to worry. But, if this doublet is within the GBW range or very near to it, this may influence the settling time of the loop. Please make sure that the parasitic capacitor associated with the diode connected MOSFET is as less as possible.

I hope I could be of some help.
 

pole zero triplet

Thanks for replying!
Actually I just have no idea how diode connected transistor gives pole-zero doublet. Can you please explain how this doublet comes.
 

doublet pole zero

I am sorry I couldnt explain properly in the previous post. The doublet is not actually due to a doide connected MOSFET only. In fact, it is due to the current mirror as a whole.

To see how the pole-zero doublet is generated, please try to do a small signal analysis of a simple differential stage with a current mirror load and single output. In the analysis, for proper results, please consider the capacitance at the gate of the diode connected MOSFET [part of current mirror].

You can expect to find a pole and a zero at exactly the same location. Make sure you dont cancel them out during the calculations.

In real world circuit, though, they would not overlap exactly and would cause settling time problems.
 

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    meghna

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doublet+pole+zero

thanks!
i'll do trhe simulation and try to understand..!
 

doublet, pole, and zero

Hi,

when ever there are two paths from input to output a zero occurs. One can observe that, when double-ended to single conversion is done using current mirror there are two paths to the ouput. So a zero occurs. Also a pole occurs at the diode connected node, for obvious reasons. It can be proved that the above zero frequency is twice the pole frequency. And this is called pole-zero doublet.

Further reading:
Razavi, Chapter 6, Pg:176
Razavi, Chapter 6, Pg:191-192
Razavi solutions, Prob. 6.15

Regards
 

doublet pole

More about pole-zero doublet:
 

spectre pole-zero

thanks for the link pixel
 

mosfet doublet

thanz for link..
yes when there will be two path for signal to flow from input to output then there will be certainly a zero will be created.
and this zero and the pole comming due to diode connected load making the doublet and they will degrade ur settling time despite of having good phase margin.
manish'
 

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