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How does a tool deal with above high and below low noise?

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arun_prabu

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Noise analysis

How does a tool deal with above high and below low noise?
 

Re: Noise analysis

Above high noise:
When the victim net is static high and the aggressor net switches from 0 to 1, there will be a noise bump in the victim net. The magnituge of this voltage bump will be greater than VDD.

Below low noise:
This occurs when the victim net is static low and the aggressor net switches from 1 to 0. The noise voltage bump in this case will be below 0.

Will SI analysis tools consider these kind of noises and tries to avoid it or ignores it?
Whether these noises affect the chip?

regards,
Arun
 

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