GDF
Full Member level 3
When the technology goes into ultra deep submicron such as 0.13um, 0.09um,
What's the major challenge of CMOS RFIC design in this era?
We know the advantage of scaling is higher cut off frequency which means
lower minimum NF of LNA inherently. But what's the other issue?
What's the major challenge of CMOS RFIC design in this era?
We know the advantage of scaling is higher cut off frequency which means
lower minimum NF of LNA inherently. But what's the other issue?