Number of bits in Folding & Interpolating ADC

Hi
In a typical folding & Interpolating architecture, there are two main parts: the Coarse Quantizer and the Fine Quantizer. In all the papers that i have seen the Coarse Quantizer is of 2Bits and the rest of bits(4 up to 6) are related with the Fine Quantizer. In this way, ADCs with bit numbers up to 8 are implemented.
My question is why the Coarse Quantizer is not implemented to provide more bits (4 for example) in order to increase the overall bit number of the ADC (up to 10bits). Unless i miss something, this would increase the available resolution of the folding & Interpolating architecture.

Thanks

The resolution of the coarse quantizer is determined by the folding factor of the folding circuits that are used. There are a number of practical aspects the limit the folding factor that can be implemented.

Anyway, high folding factors (which corresponds to a higher resolution in the coarse quantizer) are obtained by cascading folding stages: see Bult's IEEE JSSC DEC1997 paper (10b 50MHz CMOS F&I ADC).

Regards

Thanks maxwellequ

Can you please explain me how the folding factor determines the resolution of the coarse quantizer. For example, for typical folding factors 4 or 8 how many bits resolution must the coarse quantizer provide?

The folding circuit is something that you place before the latched comparator, that has a transfer function with several zero crossings -> thus now each latched comparator decides several zero crossings and, for a certain resolution, less latched comparators are needed.

Due to the cyclic nature of the folding characteristics, it is necessary to use a coarse ADC to indicate in which folding cycle lies the input signal - the cyclic code found at the output of the comparators repeats itself in every folding cycle. So the coarse resolution is determined by the number of folding cycles.

Now, as in any ADC containing a coarse and a fine subconverter, there is the necessity to guarantee the "alignment" between the coarse and fine decisions. This is done either by guaranteeing that the coarse comparators have very low offset voltages (<1LSB) or by using some kind of redundancy (i.e. a resolution larger than strictly necessary) - basically to follow a strategy similar to the one used in two-step and pipeline ADCs. Some papers in the early 90's about F&I ADCs used "bit alignment" schemes - in this case, the coarse quantizer had the minimum possible resolution, but then there was extra hardware to align the MSBs with the LSBs, in the "error prone zones". These schemes allow to have large offsets in the coarse quantizer (of course that a larger the coarse resolution implies lower offsets ...)


I advise you to read those papers. Unfortunately, it is not for me to write here everything that there is to know about that subject.