nxing
Advanced Member level 1
hello everyone,
I am trying to write a opamp model with verilog-A, there is a model from ahdlLib, however, I want something diff in with diff out and now I am stucked to how to define the output stage with Common-mode voltage. Any suggestions?
Regards,
I am trying to write a opamp model with verilog-A, there is a model from ahdlLib, however, I want something diff in with diff out and now I am stucked to how to define the output stage with Common-mode voltage. Any suggestions?
Regards,