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How to implement a PLL in a Altera Max 3064 using VHDL

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btminzon

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Hi, i need to implement a PLL in a Altera Max 3064, in VHDL, if possible, to provide a clock. Anyone knows from where can i start? thanks a lot
 

Re: PLL in FPGA

you will need external loop filter (integrator) , and vco for the pld.


clock in -----> pd (xor) ---> lpf ---> vco -------> buffer ------> clock out

<--------------------------clock divider --------<

vco = clock in * M
clock out = clock div * clock in.
 

Re: PLL in FPGA

Ok, I got it....But if i need to generate firstly a square wave, to use as a clock, to late divide ou multiply, how can i do this? thanks a lot
 

PLL in FPGA

The usual way - you will need to use a crystal oscillator for that.
 

PLL in FPGA

if u need generat a new clock frequency , u can do research on DDS.
 

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