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The importance of tap in standard cell layout

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ukint

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Hi,
I am a beginner in standard cel layout.I have observed the presence of Tap but not sure of its purpose.Can anyone letme know the importance of tap.Would appreciate if the purpose of other layers such as metal,poly,active region,contact,via is explained.

Waiting for a reply.
Thanks in advance
ukint
 

Standard Cell Layout

COuld not understand what tap u r talking about ...plz elaborate .As far as other layers r concerned u will have to read about processes used to fabricate a MOS . Read some book on IC fabrication or better read ALan hastings book.
 

Re: Standard Cell Layout

J Baker's book is also a good one.
 

Re: Standard Cell Layout

using a CADENCE Virtuoso tool, tap means highlighting/choosing a layer in the LSW when you click a certain layer in the layout editor...hope this one helps u...
 

Re: Standard Cell Layout

Hi,

Really strange question.
A mos is a 4 terminals devices: gate, drain, source and bulk.
What we call "tap" in layout is the bulk connection. It's for that you always have substrate tie and nwell tie in a standard cell.
As the others reply you need to go back or simply go to the basics to understand why a mos is a 4 terminals devices.

Franck.
 

Re: Standard Cell Layout

Thanks franck.That answered my question.
 

Re: Standard Cell Layout

franck said:
Hi,

Really strange question.
A mos is a 4 terminals devices: gate, drain, source and bulk.
What we call "tap" in layout is the bulk connection. It's for that you always have substrate tie and nwell tie in a standard cell.
Franck.
Click to expand...

The bulk is used to provide gnd/supppy to Substrate right?.

Why can't I use direct metal to connect VSS to substrate(nMOS)? Why i require p+?
 

Re: Standard Cell Layout

Prashanthanilm said:
The bulk is used to provide gnd/supppy to Substrate right?.

Why can't I use direct metal to connect VSS to substrate(nMOS)? Why i require p+?
Click to expand...

Hi,

1. Bulk in NMOS is substrate used for GROUND connection and in PMOS is Well connection to POWER.
2. To connect between Metal/Diff/Sub/Well, we need contact which are created from Tungeston material. Please read Any Fabrication Books which will explain you.


Thanks,
Basu
 

Re: Standard Cell Layout

bgangur said:
Hi,

1. Bulk in NMOS is substrate used for GROUND connection and in PMOS is Well connection to POWER.
2. To connect between Metal/Diff/Sub/Well, we need contact which are created from Tungeston material. Please read Any Fabrication Books which will explain you.
Click to expand...


Thank you basu.

I am still not clear. I don't the exact reason why p+ is used? I believe there are many advantages using tap but why can't I use direct metal to substrate?.
Yes. I am going through fab books. Can you recommend any? Also it would be better if you share some pdf's.

Thank you.
 

Hi,

The Tap layer is a pseudo layer(inversion layer).It is used for the tool to understand whether the diffusion is p+ or n+.

I can give one example,

For PMOS devices if you draw nwell ,active and tap then it becomes substrate connection.

For NMOS devices if you draw active and tap it becomes substrate connection.

Thanks
Shrikant
 

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