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18th June 2006, 20:37 #1
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What is static power dissipation and dynamic power dissipation?
what is static power dissipation and dynamic power dissipation and what is there phenomena of occurance

18th June 2006, 20:37

19th June 2006, 01:05 #2
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Re: static and dynamic
Originally Posted by libralram
Dynamic power is power consumed while the inputs are active. When inputs have ac activity, capacitances are charging and discharging and the power increases as a result. The dynamic power includes both the ac component as well as the static component.
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19th June 2006, 01:05

21st June 2006, 22:31 #3
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Re: static and dynamic
From quicklogic's application notes for static power and dynamic power in FPGA's :
Power Basics
The total power usage of an FPGA device can be broken down to total static power and total dynamic power.
PTOTAL = PSP + PDP
Static power is associated with DC current while dynamic power is associated with
AC current.
Static Power:
The FPGA static power is proportional to the static current ICC the current that flows regardless of gate switching (transistor is ON “biased” or OFF “unbiased”). DC power dissipation can be estimated by the worstcase equivalent equation:
PSP = VCC * ICC
For Eclipse devices VCC = 2.5 V and ICC = 0.140 mA.
PSP = (2.5V)(0.140mA) = 0.350 mW
Dynamic Power:
The FPGA dynamic (or active) power is related to the active current ICC[active] the current that flows when switching takes place (transistor ON “biased” and responds to smallsignals).
The AC power dissipation can be estimated by the worstcase equivalent equation:
PDP = VCC *ICC[active]
But ICC[active] = C*(dVcc/dt)
PDP = Vcc*C(dVcc/dt)
PDP = ƒ*C*Vcc²
The above equations illustrate that dynamic power is equivalent to the product of the maximum (or intended) operating frequency, the total switching loadcapacitance, and the operating voltage.
The total dynamic power consumption for any FPGA can be broken down to the total power utilized by the internal circuitry and the total power consumed by the device's inputs and outputs. For the Eclipse devices, it can be broken down further to make calculation easier to perform and understand.
In addition to logic cells, Eclipse devices have RAM blocks, ECUs, clock networks, and PLLs.
Depending on your designs, the amount of RAM, ECU, PLL, logic cell, and clock network being used can vary. It is easier to split up the power calculations accordingly.

21st June 2006, 22:31

22nd June 2006, 07:32 #4
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Re: static and dynamic
Hi,
There are three kinds of power dissipation: Static, Shortcircuit and Dynamic power dissipation. Regarding ur Static power disspation the main source of static current is Leakage Current and Reverse biased PN junction. Dynamic power dissipation invovles charging and discharging of capacitances.
Regards,
KAPIL B

21st July 2006, 15:34 #5
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Re: static and dynamic
static power dissipation occurs when there is no change in input mean circuit working and there is no chage in input then a static power dissipation occurs but when the input changes its state then at that time the dymanic power dissipation occurs
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24th July 2006, 10:51 #6
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Re: static and dynamic
Static power Dissipation: it can be tarmed as the power dissipated during steady state condition.
Dynamic power Dissipation: it can be tarmed as the power dissipated during Transient state condition.
For further details you can refer to any VLSI books
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24th July 2006, 10:51

23rd February 2007, 11:03 #7
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Re: static and dynamic
he amount of power that a chip dissipates per unit area is called its power density, and there are two types of power density that concern processor architects: dynamic power density and static power density.
Dynamic Power Density
Each transistor on a chip dissipates a small amount of power when it is switched, and transistors that are switched rapidly dissipate more power than transistors that are switched slowly. The total amount of power dissipated per unit area due to switching of a chip's transistors is called dynamic power density. There are two factors that work together to cause an increase in dynamic power density: clockspeed and transistor density.
Increasing a processor's clockspeed involves switching its transistors more rapidly, and as I just mentioned, transistors that are switched more rapidly dissipate more power. Therefore, as a processor's clockspeed rises, so does its dynamic power density, because each of those rapidly switching transistors contributes more to the device's total power dissipation. You can also increase a chip's dynamic power density by cramming more transistors into the same amount of surface area.
In addition to clockspeedrelated increases in dynamic power density, chip designers must also contend with the fact that even transistors that aren't switching will still leak current during idle periods, much like how a faucet that is shut off can still leak water if the water pressure behind it is high enough. This leakage current causes an idle transistor to constantly dissipate a trace amount of power. The amount of power dissipated per unit area due to leakage current is called static power density.
Transistors leak more current as they get smaller, and consequently static power densities begin to rise across the chip when more transistors are crammed into the same amount of space. Thus even relatively low clockspeed devices with very small transistor sizes are still subject to increases in power density if leakage current is not controlled. If a silicon device's overall power density gets high enough, it will begin to overheat and will eventually fail entirely. Thus it's critical that designers of highly integrated devices like modern x86 processors take power efficiency into account when designing a new microarchitecture.
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