Broadband, Low-Power ADC for RF applications

adc cascade folding

Hi all
I am in the starting phase of investigating wich technology (CMOS, SOI, SiGe e.t.c) and circuit architecture (pipeline, Flash, Folding Interpolating, Sigma-delta) will be suitable to implement a low-power, broadband ADC, with the following specs:

Sampling rate : from 0.1-1.5 Gsps
Analogue Input Bandwitdht : 2.5GHz
Number of bits : 10
Power consumption : 1W
Differential Analog Input voltage : 1Vpp
Power Supply : To be defined

All suggestions are welcome

Thanks

I guess a Bandwidth of 2.5 GHz is impossible. Do you mean a center frequency of 2.5 GHz and a subsampling ADC?

For a 2.5 GHz BW, you need a clock > 5 GHz...

What i mean is to sample a bandpass signal, which will be upon a carrirer. For example to sample a signal from 0.7-1.5GHz or 1.8-2.5GHz

Thanks

Perhaps you would need to use a sub-sampling ADC

Your bandwidth is too big even for a sub-sampling ADC
The sampling rate will be aroud 1G.

I have read a paper about TIQ ADC which have about 4GHz sampling rate with

65nm CMOS process.

Bandpass sampling is best approach to have reduced power consumptation for the ADC implementation.

I think most ADC implementation independend from the architecture (Flash, Folding, Interpolation, Multistage-Subranging,..) come down to about 150-500fJ/decisionstep.

So a 10bit/1GS/s have

(2^10-1)*1e9Hz*150fJ=153.5mW

These results are research for 65-130nm at the ISSCC2006.

The downsampling should be done with a aparture function which nearly covers the hole RF cycle. If the sampling switch aparture function is a ideal rectangle function you transfer pi/4 of the signal energy to your passband. If you using classic sample/hold switches the transfer is only a fraction of that. The rectangle aparature function is simply the current mixer found in any radio IC.

Hi all

Thanks for your feedback.
I believe that bandpass sampling is what i need.
From what i have read, the most suitable architecture to achieve the above mentioned specs is the folding & interpolating. However the specific architecture seems to be restricted only up to 8Bits resolution.
But what if we want 10bits with high sampling rate ? What do you think about cascade folding or sabranging architectures. Are they suitable to achieve high speed with 10bits

Thanks