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Power dissipation in Cadence IC

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gsuarez

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power dissipation cadence

Hello,

I'll like to know if the value for the power dissipation given in the Cadence IC result brower (pwr under finalTimeOP-info) for VDD is a good approximation of the dynamic power dissipation. My problem is that the average current drawn from VDD times VDD is not equal to pwr of the result browser. Any help will be appreciated.

George
 

cadence power dissipation

usually in CMOS designs

Power Dissipation α 1 / [Vdd -Vt]
Click to expand...
check in result look up table.
 

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