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Need of Hold time in Max frequency calculation?..

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varatharajan

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Whether we have taken into account the hold time while calculating the maximum frequency of digital circuits or not?..
 

No . YOu don't need to take hold time into consideration while calculating the max frequency of a circuiit . The easiest way to solve hold time violations is to add delay in the data path. So hold time is not necessary
 

If we change(increase) the clock frequency,the hold time will be violated,So there is relation between hold time and clock frequency.

Let us take an example, if setup time Ts = 2 ns , clock to Q(FF prop delay) Tpff = 0 ns and Combinatinal dealy Tp = 0 ns, Hold time Th = 2 ns .

For the above case what is the maximum clock frequency? whether hold time needs to be accounted or not?
 

As I said before fixing hold time is a relatively simple job of adding delay buffers in the data path. The reson that it is not considered during intial design of circuit is because you would like to wait until all the steps are over before adding delay buffers.
Would a circuit work if it violates hold time ? NO
 

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