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Why do we do setup and hold analysis before/after CTS?

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p.sivakumar

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setup and hold analysis

Hi

Why we are doing setup violations before CTS ? and why we are doing hold violations after CTS ?

Thanks
Sivakumar
 

Re: setup and hold analysis

hi,
you know what CTS does.. it inserts clock buffers and forms a clock tree such that clock skew from source to all flipflops are same..

If you design is not meeting setup time constraints then additional buffers leads to more complicated violations and similarly for hold violations.. if we have setup violations then this delay in clock path can also correct that violations..

Regards
Shankar
 

Re: setup and hold analysis

since set time violations are w.r.t max propogation delay and hold time violations are w.r.t min propogation delay , when buffers are inserted based on setup violations in CTS, it will mostly(not always) try to reduce hold violations too. but still there are quite a few exceptions cases where , there could be hold violation even after CTS, thus we deal them seperately after CTS.
 

Re: setup and hold analysis

because of incorrect statistical WLM at synthesis level so proper hold time info is not accurate for STA engine of synthesis tool.
 

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