Regulator to reduce supply noise to VCO??

I have a PLL diesign with a ring oscillor (CMOS) already in place. I want to put a regulator to reduce supply noise to VCO. What regulator configuration should i use? I cant have much voltage drop on the regulated voltage so that my VCO works correctly. I cant use use an LDO since i cant use an external CAP for compensation. Please suggest.
Can u suggest some reading for this?

to add to above, the VCO runs at 800Mhz and the power supply is 3.3V

thanks

That is the right approach. The high frequency PSRR is limted of the ratio of CGD of the LDO output stage PMOS and the buffer cap. Provide enough bias current for the LDO output PMOS driver stage. That set the crossover frequency of passive PSRR of the above cap ratio and the active regulation. An issue is the accuracy of the reference. If you can get 5% accuracy and the LDO need at least 250mV and the supply is minimum 1.8V-10% then the target regulation voltage is

(1.8*(1-0.1)-0.25)*(1-0.05)=1.3015V

If the ringoscillator is put into a PLL the lower frequency effect of the supply is rejected. In this case you can use a low frequency filtered reference. So take e.g. 0.85*VDD via a resistive divider and filter it with a RC ladder. An RC ladder is more effective to filter high frequency for the same area. The calculation is then

1.8*(1-0.1)-0.25=1.37V

So the area of the RC versus the 5% reference have to compared.

Thanks rfsystem,
since i have almost no headroom for a series regulator, have ever used a shunt regulator?

thanks

A shunt regulator does not help because to operate them you need first some series resistance which give you the same issue of voltage drop.

I think the issue on your side could be solved in a different way. What is your supply voltage? What is the minimum supply voltage, for the highest temperature, for worst case corner and for the highest oscillator frequency?

The solution is to use VCO control which include the regulator!

the supply voltage is 3.3V+_10%= 3to 3.6V
The VCO can work in worst case till 2.8 V.
Could you plz elaborate on the the scheme for contrl voltage regulation?

thanks

I assume that the oscillator which you use actual have to use 2.8V min but uses a specific input for frequency control. The problem with your oscillator is that the operating frequency also depend on supply voltage. Or said in another word w/o knowing your oscillator it have the supply as a second VCO input. The VDD VCO input have a sensitivity which is a significant fraction of the wanted VCO input. Second because your oscillator have a frequency control input it will slower than a simple ringoscillator on the same 2.8V.

So my suggestion is to use this simple ring oscillator. I assume for instance that it will need only 2.1V to run at the same frequency under the same condition. Now use a PMOS to feed the VDD_RINGOSC with a current. Decouple the VDD_RINGOSC with a decoupling cap. Now the gate of the PMOS is your VCO input and in fact the LDO is your VCO control. I guess that you get higher supply dependence but the VDD noise rejection depend on your application.