xilinx's answer's database not very useful

the network is completely unrouted

THESE are the errors i am getting while running ASSEMBLY PHASE implementation
of the PARTIAL RECONFIGUARTION FLOW..i have tried the answers database to debug it ,,but it doesn seem to work out..........

please help out here!!!!!

Running DRC.
WARNINGhysDesignRules:367 - The signal <fixed/clk> is incomplete. The signal
does not drive any load pins in the design.
WARNINGhysDesignRules:367 - The signal <fixed/sync> is incomplete. The signal
does not drive any load pins in the design.
ERRORhysDesignRules:10 - The network <clk_IBUF> is completely unrouted.
ERRORhysDesignRules:9 - The network <GLOBAL_LOGIC0> is only partially routed.
ERRORhysDesignRules:9 - The network <GLOBAL_LOGIC1> is only partially routed.
ERRORhysDesignRules:9 - The network <decode_out_OBUF> is only partially
routed.
ERRORhysDesignRules:10 - The network <reconfig/vit_3/N2184> is completely
unrouted.
ERRORhysDesignRules:10 - The network <reconfig/vit_3/N52222> is completely
unrouted.
ERRORhysDesignRules:794 - Component reconfig/reconfig/vit_3/N2184 is not
placed.
ERROR:Bitgen:25 - DRC detected 7 errors and 2 warnings.

errorhysdesignrules:9

try to open a WEBCASE.

physdesignrules:10

Hello Deepa, did you ever figure out why you were getting that "completely unrouted" error? How does someone fix a problem like this. I am also getting that error.

the signal is incomplete unrouted

Reduce level of logic in your design - try something smaller. Maybe software simply can't place & route. Also, forget about warnings, they just say that two of your signals do nothing (so you may remove them ).

xilinx physdesignrules 10 bitgen

The above error is because you arent driving any load using the above pins just remove the pins which arent used for logic design

the network is completely unrouted

ERRORhysDesignRules:10 - The network <clk_IBUF> is completely
unrouted.

Click to expand...

This is due to the fact that you've declared an IOB component both in design and in constrainst file, but you may've failed to load that with a source...If the IO port is defined as OUT mode, and if you fail to load it, this error and warning appear after the implementation process. If you start driving the loadless signals with a source, all these errors will disappear,I believe..Put your feedback if things really are helpful
Regards

Added after 5 minutes:

kalyansrinivas said:

The above error is because you arent driving any load using the above pins just remove the pins which arent used for logic design

Click to expand...

If you simply remove the pin definitions in the user constraints file, the possibilities are that the design may route the IO to an unassigned port though you mayn't use that pin for your part but it may affect the hardware sometimes. If you decide not to use a port, remove both in UCF as well as in your design.Because removing the IO from your constraints file will not generate any error,but it will make the design to assign any pins other than the ucf points to....I have got such problems many time(always wondered sometimes why the unconnected led for my project glew )Correct me if I'm wrong!

physdesignrules:367

Your posts were all very helpful and I was able to solve my problem. I am using the Xilinx Spartan3A DDR2 development board, and I am very new to FPGA's.

I've attached the error message that the Xilinx ISE was generating. After reading your comments, I took a look at the electrical schematics for this board and found out that the LCD_E, LCD_RS, LCD_WS, and LCD_DB(0 to 7) were all IO ports. In my VHDL code, I defined them as output ports only.

I changed these ports to IO which solved the problem. Thanks for leading me in the right direction guys. Much appreciated!