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Verilog Instruction for finding absolute value!

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verilog absolute value

hi...
how to find the absolute value using verilog language...
i hav got fft_real_ value and fft_imag_value...
now i got to find the fft_out_value...

Does this wok?
fft_out <= (((fft_real_out*fft_real_out) + (fft_imag_out*fft_imag_out))**1/2);
 

absolute value verilog

Well, I am not familiar with verilog, but you should have some software to perform simulations, don't you?
I use Active HDL, you only need to know what number format you are using, and then perform the operation. Just take care of the word length, remember that a multiplier returns twice the length of the operators, i.e. Multiplying A2.14 * B 2.14 = C4.28, A and B are 16-bit numbers in format 2.14, C is a 32-bit number in format 4.28. You can perform your simulation and check if the result is correct.
In Active you can display numbers in decimal, binary, hexadecimal, and octal, also in unsigned or signed numbers.
Hope this helps you.
 

verilog absolute

well my question is how to calculate power or square root operation... i think there is no power opertor in verilog HDL. where in VHDl we use **.
i want to do the above calculation and i want the verilog code for doing that...
 

absolute value in verilog

Tthere is no power opertor or square root operation in verilog HDL. square root operation is difficult to design and cost a lot of resources.

the absolute value(b=|a|):

reg a [31:0];
reg b [31:0];
always@(*)
begin
if (a[31]==1'b1)
b[31:0]={1'b1,a[30:0]};
else b [31:0]=a [31:0];
end
 

verilog abs

Yes, there is no square root operation neither in VHDL. I was told that square root operation is performed using a Succesive Aproximation Register, and a comparator. I have some code in VHDL that performs the square root of an n-bit number, let me know if it would work for you.
 

verilog square root

Its possible to calculate the square root in verlog HDL, you can always use aproximations.

Refer "Digital Signal Procesing" By John G Proakis Page #93.

S{n} = (S{n-1} + A / S{n-1}) / 2
'A' is the number.
This is an iterative equation. S{n-1} is the initial guess (use some constant) of square root. When S{n} and S{n-1} are approximately equal. Take S{n} as the square root.

You have to implement this in VerilogHDL.
 

absolute verilog

maybe it can be synthesized ,but i think it can't work well because synthesise result is not good.
 

Re: verilog absolute value

module abs(
input [7:0] a,
input [7:0] b,
output [7:0] res
);

wire [7:0] tmp;
assign tmp = a-b;
assign res = (~tmp[7:0])+8'h01;
endmodule
 

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