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how to design a synthesizable memory in verilog

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samuel_raja_77

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1.The design rquires to initialize a memory of depth 5k with differnent valued for each location
2. need to read the data from memory and compute value based on the input variables
3.need to write the computed value in another memory
4.is it good to have all the process in a single module
 

You can use flip-flop array to build memory. But the area is costly.
 

You must design memory by circuit level, not verilog
. Verilog only can be used in model desicraption.
 

Yes .. you can use d-flip-flop to build a register file ..
But you should listening to what Mr. Lin told ..
 

A general rule of thumb that is valid for most processes is that upto 1K bit elements use registers, otherwise use a real SRAM based memory.

5K that you mention is too much and although it may look ok even after synthesis
it will cause a lot of routing congestion problems especially if you put scan chains
 

In FPGA some tools support memory synthesis.
In Asic, must use IP.
 

I guess you are trying to verify ur dut that is possbily some data processing unit. Where u would like to read data , process it and write back to memory.

If this true, then u can use the behavioural memory models, where ur can down load them from internet, or you can also use text based test bench where u read the data in one line from text file and also write back the data to the text file.
 

so in the real time how the memories is being designed could any one help me in modeling the memory by providing some links ...or some suggesstion
 

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