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set up and hold time?

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abhineet22

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aviral mittal

in setup time and hold time which one is critical for estimating maximum clock frequency of a circuit?and why?
 

fmax setup time

Both setup and hold times added together must be less than the clock period.
 

maximum clock frequency set up time of operation

setup time
 

determine the minimum setup time

only setuptime is used for calculating clock frequency. hold time does not comes into play. hold time violation occurs when there is very minimum propagation delay. setup time deals with max. propagation delay.. as clock frequency depends on propagation delay of combinational circuit present in between sequential..
only setup time is considered for calculating clock frequency.
 

digital integrated circuit jon rabey

Setup and hold added together determine the minimum window in which data must remain stable in order for valid sampling to occur. These times are relative to the clock pulse.
 

sequential setup hold max frequency

Hi ,

If fail hold time, the circuit cannot run in any frequency, not even 1hz.

If hold is not failing, then it is meaningful to talk about the max freq the circuit can run.

Regards,
Eng Han
www.eda-utilities.com
 

maximum clock frequency with setup and hold time

if hold time is violated,the chip has to be discarded,but,it is only setup time that controls freq of operation
 

setup and hold time for digital design

to the critic path, the delay is max, the hold time is met,
the setup time may be the violated,
So, the setup time is critical
 

what is a setup time in a circuit

Hi,

> to the critic path, the delay is max, the hold time is met,
> the setup time may be the violated,
> So, the setup time is critical

I can't help but has to reply again. If hold time fail on any timing path, it doesn't matter if you meet all the "critical path". The chip will not work if hold time fail.

I agree that critical path for max delay is difficult to meet. But I will also argue that the number of criitical path for hold is much more in number. For example, every scan path is a potential for hold violation.

Regards,
Eng Han
ww.eda-utilities.com
 

what is clock skew & slack + rabey

setup time is critical for freq
hold time is not
but it is also critical in other part
right?
 

hold timing fails, design

setup & hold time are limitations for a flip-flop to work normally.
They are two of a flip-flop characters.

The Max frequence is based on not only the flip-flop characters, but also the other combine logic within the data-path.
And the setup&hold time is not critical, for we could hardly to change it, unless we change the library type, such as from high-vt to low-vt.
The combine logic datapath, including device and wires, is much more critical, for we could re-new our rtl , optimize the logic, remap the cells and/or re-place & route the device/wires to met the timing slack.

And more, the max frequence is determine by the worst datapath in 1 clock domain.
 

low vt setup time

only setup time is used
because the max frequency is based not only on the flipflop characterstics but also on the combinational logic
 

calculating clock frequency from setup and hold

i agree with leeenghan.if you design cann't meet the hold time,you design cann't work.the max frequence is related to the filpflop not only,but also the delay of combiantion logic between two flipflop.if you can optimize the conbination logic.reduce the delay of it.you can increase the max frequence!
 

When we are calculating the max.freq of the circuit will account the Setup Time...

Fmax= 1/(tc-q+tcombo+tsetup)

Fmax----> Max freq of the circuit..
tc-q------> Time ( clk-to- Q)
tcombo--> Time ( COmbinational dealy)
tsetup---> Setup time of the destination flop...
 

hold violation normally fixed in the layout stage
 

You better read Digital Design by John Rabaay ,
It seems it is a very basic question.
 

Hold time does not count towards the frequency of operation.
Fmax = 1/(tpd_clk2q+tsetup+tpd_combilogic)
If you look at a cmos circuit of a flip flop, then you will see that tpd_clk2q is always greater than thold. In fact it can be shown that tpd_clk2q is always thold + something. So it 'encapsulates' the hold time. So once tpd_clk2q is considered in calculating Fmax, hold time is automatically taken care of.
If you consider a hypothetical situation where tpd_clk2q is less than hold time, then Fmax will be calcualted using thold as well. But this is not possible in a normal circuit of a flip flop.
Hence hold time is never taken into account while calculating Fmax
Hope this helps
Kr,
Aviral Mittal
http://www.vlsiip.com
 

I Totally agree aviral Mittal.This is the perfect answer. Normally it is assumed that hold time is encapsulated in tc clok to q delay and never taken into account for calculation of maximum frequency. But this is not true. Because if hold time is violated then Flip flop operation will not be correct. and then there shall be introduction of delay in data path which shall reduce the frequency of operation.
 

ya u are right. but

the hold time comes such that

Thold>= min_propagationdelay of combinational logic;

see digital integrated circuits rabeay for details


Regards
Shankar
 

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