accumulator VHDL concurrency issue

vhdl concurrency

Hello,

I found from Altera's website the following multiplier-accumulator. I doubt it will work because the delta propagation. In the code:
pdt_reg <= a_reg*b_reg;
adder_out <=adder_out +pdt_reg;
will the updated pdt_reg be added to adder_out withou the effect of delta delay? How to handle this?


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY sig_altmult_accum IS
PORT (
a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clk: IN STD_LOGIC;
accum_out:OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
) ;
END sig_altmult_accum;

ARCHITECTURE rtl OF sig_altmult_accum IS
SIGNAL a_reg, b_reg : signed (7 DOWNTO 0);
SIGNAL pdt_reg : signed (15 DOWNTO 0);
SIGNAL adder_out : signed (15 DOWNTO 0);
BEGIN
PROCESS (clk)
BEGIN
IF (clk'event and clk = '1') THEN
a_reg <= SIGNED (a);
b_reg <= SIGNED (b);

pdt_reg <= a_reg * b_reg;
adder_out <= adder_out + pdt_reg ;
END IF;
END process;

accum_out <= std_logic_vector(adder_out);
END rtl;