minor error in vhdl code????

hi frenz,
i had run this code there is no error but lots of warning and also i have doubt that it might be wrong this code for register array and its mapping to byte and bit register....
All outputs of the instance <regw> of the block <byte_register> are unconnected in block <regarray>.
""This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <regz> of the block <byte_register> are unconnected in block <regarray>.""
this type of warning i am getting after running this code........can any one help me


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity regarray is
port( mux :inout std_logic_vector(7 downto 0);
selreg : in std_logic_vector(3 downto 0);
clock : in std_logic;
reset : in std_logic;
enable1:in std_logic;
regrdwr:in std_logic;
pcinc:in std_logic;
addressbuffer : out std_logic_vector(7 downto 0);
dataaddbuffer: out std_logic_vector(7 downto 0));
end regarray;

architecture rtl of regarray is
component byte_register
port (
Reset : in std_logic;
Enable : in std_logic;
Clock : in std_logic;
Datain : in std_logic_vector(7 downto 0);
Dataout : out std_logic_vector(7 downto 0) );
end component;
component bit16_register
port (
Reset : in std_logic;
Enable : in std_logic;
Clock : in std_logic;
Datain : in std_logic_vector(15 downto 0);
Dataout : out std_logic_vector(15 downto 0) );
end component;
signal spc:std_logic_vector(15 downto 0):="0000000000111111";
signal pcc:std_logic_vector(15 downto 0):="0000000000000000";
signal temp_data : std_logic_vector(7 downto 0);
signal temp_w : std_logic_vector(7 downto 0);
signal temp_z : std_logic_vector(7 downto 0);
signal temp_b : std_logic_vector(7 downto 0);
signal temp_c : std_logic_vector(7 downto 0);
signal temp_d : std_logic_vector(7 downto 0);
signal temp_h : std_logic_vector(7 downto 0);
signal temp_l : std_logic_vector(7 downto 0);
signal temp_e : std_logic_vector(7 downto 0);
signal temp_pc : std_logic_vector(15 downto 0);
signal temp_sp : std_logic_vector(15 downto 0);
signal enw,enz,enb,enc,en_d,ene,enh,enl,en_sp,en_pc:std_logic;
begin
regw: byte_register port map(reset,enw,clock,temp_data,temp_w);
regz: byte_register port map(reset,enz,clock,temp_data,temp_z);
regB: byte_register port map(reset,enb,clock,temp_data,temp_b);
regC: byte_register port map(reset,enc,clock,temp_data,temp_c);
regD: byte_register port map(reset,en_d,clock,temp_data,temp_d);
regE: byte_register port map(reset,ene,clock,temp_data,temp_e);
regH: byte_register port map(reset,enh,clock,temp_data,temp_h);
regL: byte_register port map(reset,enl,clock,temp_data,temp_l);
stackP: bit16_register port map(reset,en_sp,clock,spc,temp_sp);
PC: bit16_register port map(reset,en_pc,clock,pcc,temp_pc);

process(enable1,clock,mux,selreg,regrdwr,reset)
begin
if (reset='1' and enable1 ='0')then
addressbuffer<="00000000";
dataaddbuffer<="00000000";
elsif reset='0'and enable1='1' then --and clock'event and clock='1'then
case selreg is
when "0000"=> if clock'event and clock ='1'then
if regrdwr='0'then--and clock'event and clock ='1'then
enw<='0'after 1 ns;
mux<=temp_w after 1 ns;
elsif regrdwr='1' then--and clock'event and clock='1'then
enw<='1'after 1 ns;
temp_data<=mux after 1 ns;
end if;
end if;


when "0001"=>if clock'event and clock ='1'then
if regrdwr='0'then--and clock'event and clock ='1'then
enz<='0'after 1 ns;
mux<=temp_z after 1 ns;
elsif regrdwr='1'then-- and clock'event and clock='1'then
enz<='1'after 1 ns;
temp_data<=mux after 1 ns;
end if;
end if;
when "0010"=> if clock'event and clock ='1'then
if regrdwr='0'then--and clock'event and clock ='1'then
enb<='0'after 1 ns;
mux<=temp_b after 1 ns;
elsif regrdwr='1'then --and clock'event and clock='1'then
enb<='1'after 1 ns;
temp_data<=mux after 1 ns;
end if;
end if;
when "0011"=>if clock'event and clock ='1'then
if regrdwr='0'then--and clock'event and clock ='1'then
enc<='0'after 1 ns;
mux<=temp_c after 1 ns;
elsif regrdwr='1'then --and clock'event and clock='1'then
enc<='1'after 1 ns;
temp_data<=mux after 1 ns;
end if;
end if;
when "0100"=> if clock'event and clock ='1'then
if regrdwr='0'then--and clock'event and clock ='1'then
en_d<='0'after 1 ns;
mux<=temp_d after 1 ns;
elsif regrdwr='1'then --and clock'event and clock='1'then
en_d<='1'after 1 ns;
temp_data<=mux after 1 ns;
end if;
end if;
when "0101"=> if clock'event and clock ='1'then
if regrdwr='0'then--and clock'event and clock ='1'then
ene<='0'after 1 ns;
mux<=temp_e after 1 ns;
elsif regrdwr='1'then-- and clock'event and clock='1'then
ene<='1'after 1 ns;
temp_data<=mux after 1 ns;
end if;
end if;
when "0110"=>if clock'event and clock ='1'then
if regrdwr='0'then--and clock'event and clock ='1'then
enh<='0'after 1 ns;
mux<=temp_h after 1 ns;
elsif regrdwr='1'then-- and clock'event and clock='1'then
enh<='1'after 1 ns;
temp_data<=mux after 1 ns;
end if;
end if;
when "0111"=>if clock'event and clock ='1'then
if regrdwr='0'then--and clock'event and clock ='1'then
enl<='0'after 1 ns;
mux<=temp_l after 1 ns;
elsif regrdwr='1'then --and clock'event and clock='1'then
enl<='1'after 1 ns;
temp_data<=mux after 1 ns;
end if;
end if;
when "1000"=> if clock'event and clock ='1'then
if regrdwr='0'then--and clock'event and clock ='1'then
en_sp<='0'after 1 ns;
addressbuffer<=temp_sp(15 downto 8) after 1 ns;
dataaddbuffer<=temp_sp(7 downto 0) after 1 ns;
elsif regrdwr='1' then--and clock'event and clock='1'then
en_sp<='1'after 1 ns;
spc<=temp_sp-"0000000000000001" after 1 ns;
temp_data<=mux after 1 ns;
end if;
end if;
when "1001"=>if clock'event and clock ='1'then
if regrdwr='0'then--and clock'event and clock ='1'then
en_pc<='0'after 1 ns;
addressbuffer<=temp_pc(15 downto 8) after 1 ns;
dataaddbuffer<=temp_pc(7 downto 0) after 1 ns;
elsif regrdwr='1'then-- and clock'event and clock='1'then
en_pc<='1'after 1 ns;
spc<=temp_pc+"0000000000000001"after 1 ns;
end if;
end if;
when "1010"=> if clock'event and clock ='1'then
if regrdwr='0'then--and clock'event and clock ='1'then
enh<='0'after 1 ns;
enl<='0'after 1 ns;
addressbuffer<=temp_h after 1 ns;
dataaddbuffer<=temp_l after 1 ns;
end if;
end if;
when others=>
addressbuffer<="XXXXXXXX";
dataaddbuffer<="XXXXXXXX";
mux <="XXXXXXXX";
end case;
end if;
end process;
end rtl;




library iEEE;
use iEEE.std_logic_1164.all;

entity bit16_register is
port (
Reset : in std_logic;
Enable : in std_logic;
Clock : in std_logic;
Datain : in std_logic_vector(15 downto 0);
Dataout : out std_logic_vector(15 downto 0) );
end bit16_register;

architecture behav of bit16_register is

begin
process(Clock,Reset, Datain)
begin
if(Reset='1') then
Dataout<="0000000000000000";
elsif(Reset='0' and Enable = '1' and clock = '1' and clock'event) then
Dataout<=Datain;
end if;
end process;
end behav;

library iEEE;
use iEEE.std_logic_1164.all;

entity byte_register is
port (
Reset : in std_logic;
Enable : in std_logic;
Clock : in std_logic;
Datain : in std_logic_vector(7 downto 0);
Dataout : out std_logic_vector(7 downto 0) );
end byte_register;

architecture behav of byte_register is

begin
process(Clock,Reset, Datain, Enable)
begin
if(Reset='1') then
Dataout<="00000000";
elsif(clock = '1' and clock'event) then
if (Enable = '1') then
Dataout<=Datain;
end if;
end if;
end process;
end behav;