abhineet22
Advanced Member level 4
after running this code the error is bad synchronous description..........
can any one help me....
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity accumulator is
port( data : inout std_logic_vector(7 downto 0);
rd_wr : in std_logic; --0=read,1=write
clock : in std_logic;
reset : in std_logic
);
end accumulator;
architecture rtl of accumulator is
signal temp_data_in:std_logic_vector(7 downto 0);
signal temp_data_out:std_logic_vector(7 downto 0);
component byte_register is
port (
Reset : in std_logic;
Enable : in std_logic;
Clock : in std_logic;
Datain : in std_logic_vector(7 downto 0);
Dataout : out std_logic_vector(7 downto 0) );
end component;
begin
acc: byte_register port map(reset,rd_wr,clock,temp_data_in,temp_data_out);
process(clock,reset)
begin
if clock'event and clock='1'and reset='0'then
if rd_wr='0'then
data<=temp_data_out;
else
temp_data_in<=data;
end if;
else
data<=temp_data_out;
end if;
end process;
end rtl;
library iEEE;
use iEEE.std_logic_1164.all;
entity byte_register is
port (
Reset : in std_logic;
Enable : in std_logic;
Clock : in std_logic;
Datain : in std_logic_vector(7 downto 0);
Dataout : out std_logic_vector(7 downto 0) );
end byte_register;
architecture behav of byte_register is
begin
process(Clock,Reset, Datain)
begin
if(Reset='1') then
Dataout<="00000000";
elsif(Reset='0' and Enable = '1' and clock = '1' and clock'event) then
Dataout<=Datain;
end if;
end process;
end behav;
can any one help me....
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity accumulator is
port( data : inout std_logic_vector(7 downto 0);
rd_wr : in std_logic; --0=read,1=write
clock : in std_logic;
reset : in std_logic
);
end accumulator;
architecture rtl of accumulator is
signal temp_data_in:std_logic_vector(7 downto 0);
signal temp_data_out:std_logic_vector(7 downto 0);
component byte_register is
port (
Reset : in std_logic;
Enable : in std_logic;
Clock : in std_logic;
Datain : in std_logic_vector(7 downto 0);
Dataout : out std_logic_vector(7 downto 0) );
end component;
begin
acc: byte_register port map(reset,rd_wr,clock,temp_data_in,temp_data_out);
process(clock,reset)
begin
if clock'event and clock='1'and reset='0'then
if rd_wr='0'then
data<=temp_data_out;
else
temp_data_in<=data;
end if;
else
data<=temp_data_out;
end if;
end process;
end rtl;
library iEEE;
use iEEE.std_logic_1164.all;
entity byte_register is
port (
Reset : in std_logic;
Enable : in std_logic;
Clock : in std_logic;
Datain : in std_logic_vector(7 downto 0);
Dataout : out std_logic_vector(7 downto 0) );
end byte_register;
architecture behav of byte_register is
begin
process(Clock,Reset, Datain)
begin
if(Reset='1') then
Dataout<="00000000";
elsif(Reset='0' and Enable = '1' and clock = '1' and clock'event) then
Dataout<=Datain;
end if;
end process;
end behav;