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ADC design static error

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ee484

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Hi, I am curious how to determine loop-gain for 10bit ADC design.
Since static error is 1/To (To: DC loop gain), for 10bit ADC, is error should be less than VFS/2^10 or 0.5*VFS/(2^10).

I heard VFS/2^10 is being used for static error, but I think a half of VFS/2^10 makes more sense...
 

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