jimjim2k
Advanced Member level 3
Hi
The Dalton project focuses on the design of Intellectual Property (IP, or core) based embedded computing systems, i.e., systems-on-a-chip. Its present focus is on a "parameterized system-on-a-chip design" approach. In this approach, an application, such as a digital camera, is designed first by selecting an existing reference design consisting of a collection of predesign processor-level components (cores), second by repeatedly configuring the programmable parts of those cores for the desired application (e.g., writing software and setting parameter values) and executing the design to verify functionality, and finally by generating final chip. Our current emphasis is on devising a methodology and tools to support the exploration of the impact of various parameter values (e.g., cache size, bus size, DMA block transfer size, arbiter schemes, etc.) on design metrics like power and performance, so that a designer can "tune" the architecture to a specific application (and vice-versa). We are also working on developing new architectural constructs specifically intended for such tuning, as well as methods for an architecture to tune itself. The project is being carried out in the Department of Computer Science and Engineering at the University of California, Riverside, under the direction of Prof. Frank Vahid. The project is named after the chemist John Dalton.
1. h**p://www.cs.ucr.edu/~dalton/
(And ... some good archives)
2. h**p://www.cs.ucr.edu/~dalton/summer2000/
* -> t
tnx
The Dalton project focuses on the design of Intellectual Property (IP, or core) based embedded computing systems, i.e., systems-on-a-chip. Its present focus is on a "parameterized system-on-a-chip design" approach. In this approach, an application, such as a digital camera, is designed first by selecting an existing reference design consisting of a collection of predesign processor-level components (cores), second by repeatedly configuring the programmable parts of those cores for the desired application (e.g., writing software and setting parameter values) and executing the design to verify functionality, and finally by generating final chip. Our current emphasis is on devising a methodology and tools to support the exploration of the impact of various parameter values (e.g., cache size, bus size, DMA block transfer size, arbiter schemes, etc.) on design metrics like power and performance, so that a designer can "tune" the architecture to a specific application (and vice-versa). We are also working on developing new architectural constructs specifically intended for such tuning, as well as methods for an architecture to tune itself. The project is being carried out in the Department of Computer Science and Engineering at the University of California, Riverside, under the direction of Prof. Frank Vahid. The project is named after the chemist John Dalton.
1. h**p://www.cs.ucr.edu/~dalton/
(And ... some good archives)
2. h**p://www.cs.ucr.edu/~dalton/summer2000/
* -> t
tnx