Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

variable dutycycle with fixed frequency digital logic

Status
Not open for further replies.
D

deb_mallik

Banned
Joined
Jan 24, 2006
Messages
44
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,286
Activity points
0
can any one suggest variable dutycycle with fixed frequency digital logic circuit
thanks in advanced
 

Does your system only use one edge trigger??
 

PWM (pulse width modulation) output contains fixed frequency variable dutycycle wavwform.
It is vaery simple to generate PWM output. Take a shift register and rotate the data for each clk. Fead the output of the shiftregister back to the input of register through an XOR gate.

It is very simple and you can try it.
 

Check the code below!

Code: 
module pwm(clk, reset, data, led);
   input clk;
   input reset;
   input [7:0] data;
   output      led;

   reg         led;
   reg [7:0]   pwm_count;

always @(posedge clk or posedge reset) begin
   if (reset) begin
      pwm_count <= 0;
      led <= 0;
   end else begin
	  pwm_count <= pwm_count + 1;
	  if ( pwm_count <= data ) begin
		 led <= 1;
	  end else begin
		 led <= 0;
	  end
   end
end

endmodule
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top