Thread: what is mmmc mode in timing analysis

Hi guys ..
what's Cadence's tool for STA ? .. and also what's its tool for DFT ? .. or both are embedded in RC ? ..
I know about Synopsys having both STA & DFT functions in DC and also having stand alone PrimeTime and DFT Compiler ..
so, is it the same with cadence ?

hi,
cadence STA tools is named CTE which is embeded in buidgates and encounter. dft tool is encounter test or rc.

Originally Posted by linuxluo

hi,
cadence STA tools is named CTE which is embeded in buidgates and encounter. dft tool is encounter test or rc.

is it enough to use rc in dft ? .. or should I use encounter test ? .. and is encounter test embedded in SoC Encounter ?

Added after 2 hours 6 minutes:

By the way .. I'm a little bit confused ! .. I got some other information about STA in cadence .. people say there is a tool called Pearl .. what about it ? .. is it still there or obsulate .?
I also heard about conformal which I was thinking of it as a formal verification tool, but seems that it's working as an STA tool !!!!!!!! .. here is a part of a document representing Cadence Conformal :
"
Part of the Cadence® Encounter™ digital IC design platform, Encounter Conformal® Constraint Designer automates the validation and modification of constraints and ensures that timing constraints are valid throughout the entire design process.
Based on a world-class formal engine, Encounter Conformal Constraint Designer
checks design constraints for correctness, functionally validates exceptions, checks
hierarchical constraints for consistency, and generates timing exceptions. By
pinpointing real design issues quickly and accurately, Encounter Conformal
Constraint Designer helps designers achieve rapid timing closure.
"

Cadence STA tool:
CTE (common timing engine): static timing analysis
+ SignalStorm: delay calcularor (using ECSM library)
+ Celtic: crosstalk analysis
= IR-aware timing/crosstalk analysis tool
------------------------------------------------------------------------------------

Cadence DFT tool:
- 1) DFT synthesis: (scan synthesis)
BuildGate, or RTL Compiler

- 2) MBIST, ATPG (automatic test pattern generation), Test-compression, and Diagnostic engine
Encounter Test
--------------------------------------------------------------------------------------

Conformal family contains
1) Equivalence check
Conformal LEC/ASIC/Ultra/Low Power
2) Timing constraint (SDC file) check & generation
Conformal Constraint Designer (CCD) --> NOT a STA tool.
(http://www.cadence.com/products/digi...mal/index.aspx)
---------------------------------------------------------------------------------------

Hi,

PEARL is the STA tool from Cadence

Originally Posted by carrot

Hi,

PEARL is the STA tool from Cadence

is PEARL part of SoC Encounter ?

pearl is a stand alone program!
but PrimeTime is the popest STA tool in the world!

1) Pearl is Cadence's OLD static timing analysis tool.

2) Right now, CTE (common timing engine) is STA engine for BG/PKS/FE.
(RC uses its own timing engine.)

3) Pearl technology has been integrated into CTE.
-----------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------
Tool migration:
Pearl --> CTE + SignalStorm
BuildGate --> RTL Compiler
CTGen --> FE-CTS
Silicon Ensemble + PKS --> FE + FE-GPS + NanoRoute

Hi All,
Cadence has come out with a New STA tool called Encounter Timing System (ETS). It is their answer to PT which is from Synopsys.
Please go through this article.
http://deepchip.com/items/0457-03.html.

Thanks

For DFT, Cadence has Encounter Test which can provide Test synthesis, Test Generation and Diagnostic.
You can also use RTL Compiler to do the test synthesis.

Cadence timing sign-off tools
ETS-encounter timing sign-off

It is simillar to PT.
Now a days most of the company accepted to ETS is must better that PT. let me know if any having doubt on ETS

ETS (Encounter Timing System) is the STA tool from Cadence
the DFT structre is implemneted in RC and the coverage can be obtained by ET

I think that the MMMC(Multi mode Multi corner) options and the possibility to call CCD from the tool are two great features of ETS
There is another interesting feature in ETS that allows the user to group paths and debug timing. it looks like a useful and important feature to debug timing in complex designs in the future. Timing violations can be grouped and debugged separately, so the designer will have a better view of the real problems of the design.

Added after 52 seconds:

I think that the MMMC(Multi mode Multi corner) options and the possibility to call CCD from the tool are two great features of ETS
There is another interesting feature in ETS that allows the user to group paths and debug timing. it looks like a useful and important feature to debug timing in complex designs in the future. Timing violations can be grouped and debugged separately, so the designer will have a better view of the real problems of the design.

Added after 2 minutes:

I think that the MMMC(Multi mode Multi corner) options and the possibility to call CCD from the tool are two great features of ETS
There is another interesting feature in ETS that allows the user to group paths and debug timing. it looks like a useful and important feature to debug timing in complex designs in the future. Timing violations can be grouped and debugged separately, so the designer will have a better view of the real problems of the design.

PT also has muti mode multi corner.