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What is the default value for VCS?(question on Verilog code)

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yuenkit

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`resetall for vcs

if my verilog code contains
`resetall

which from the documentation said it will reset to the default compiler directive value of vcs


What is default value for VCS? where can i get the default value?


`uselib (without any arguments)
what does it do? Does it swith off the previous `uselib in your design? What does it mean by switch off? Does it mean that it will stop using the libraries being referenced?
 

Re: `resetall for vcs

hi,
check vcs user guide or vcs reference manual.
 

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