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- 18th March 2006, 07:37 #1

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## high-z output

Hi,

How do i model high-z output in verilog-A ?

Currently I'm modeling it to output = 0, but it is causing conflict when i cascode them at top level (error = output connected to another output).

Currently the method i'm using is

:

:

vout = 0;

:

:

V(OUT) <+ vout ;

......

With what value should i replace the '0' with in order to get a high-z output?

Thanks a million for ur help !!!!!

- 18th March 2006, 07:37

- 18th March 2006, 13:26 #2

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## verilog high z output

Zout = 1e+15;

V(OUT) <+ I(OUT) * Zout;[size=2]Best Regards,[/size]

[size=2]Hughes[/size]

- 18th March 2006, 13:49 #3

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## switch modeling verilog-a

Hughes,

Thanks for ur advice. But I'm still having the same problem. It seems that the formula u gave still yeilds a voltage value. How do i model it so that the circuit sees a disconnected output (i.e. high-z state) ?

- 18th March 2006, 13:49

- 19th March 2006, 02:31 #4

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## switch modeling veriloga

A disconnected output also has a voltage value. To see the high-z effect, you should connect another low-z driving source to this node.

[size=2]Best Regards,[/size]

[size=2]Hughes[/size]

- 19th March 2006, 09:19 #5

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## verilog high z

hello,

as far as i understand u need to model open circuit , so i think u should make input current equal zero and no conditions on voltage "u confused me a little bit, as what i understand is that V(out)=0 is short cicuit not open circuit ,so plz post the solution that u will find".

btw i think if u just make the output node as a voltage node and not electrical it wont draw any current "not sure".

regards,

a.safwat

- 19th March 2006, 15:42 #6

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## Re: Modeling high-z output in verilog-A

Originally Posted by**Hughes**

Added after 2 hours 34 minutes:

then again, is there any method to disable output in verilogA?

- 20th March 2006, 05:21 #7

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## Re: Modeling high-z output in verilog-A

Originally Posted by**steve_mac**

Originally Posted by**steve_mac**[size=2]Best Regards,[/size]

[size=2]Hughes[/size]

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