What type of LDO structure for digital circuits in a SoC?

So, Which LDO structure is the best for digital circuits?
(Digital circuits usually make large current spikes)
Have you ever seen a solution avoid the external capacitor (CMOS only solution)?
I don't want an external capacitor beside the SoC.

Re: What type of LDO structure for digital circuits in a SoC

Hi,
you have two general choice for designing an LDO regulator, see attachment. Structure (a) doesn’t need a charge pump, but at high-frequencies the output node is high-impedance (because loop-gain is very low at high frequency) so it cannot damp noise due to digital circuits on power supply (You can use a big external cap to reduce the output impedance at high-frequency, which you don’t like). Also the structure may have stability problem.

Structure (b) is a little bit more complicated to design, but has much better features. Better stability and low output impedance even at high-frequencies, wider gain-bandwidth product.
Since this structure has low output frequency even at high frequencies, it can better damp noise due to digital circuits.

So I suggest structure (b).

OpAmp

Re: What type of LDO structure for digital circuits in a SoC

Hi,
In the first solution : is it a positive feedback?
In the second solution (with the charge pump): Are there any article about this structure? I can' t find in IEEE this charge pump soluton.

Have you ever been design a DFC type LDO? (Damp factor control frequency compensation)

Thanks.

Re: What type of LDO structure for digital circuits in a SoC

In the first solution : it is a negative feedback because output common source PMOS cascade is inverting.
Second solution is used for very low voltage regulator as PMOS gate voltage is not enough in this case.

Re: What type of LDO structure for digital circuits in a SoC

Hello,

In the second solution: What's the function of the charge pump? It's a voltage doubler ( increase the supply voltage)?

Hi,

In the second solution, because of the Vgs voltage drop of transistor Mpass, we cannot achieve a low-drop out voltage regulation (because Vdd should be at least Vgs volt below the power supply voltage of the Error Amplifier). As a result a simple charge pump is
required to generate a supply voltage (higher than VDDH) for the Error Amplifier. For charge pump, you can use a simple Dickson charge-pump or a voltage doubler.

OpAmp

use charge pump to control source follower is good

Re: What type of LDO structure for digital circuits in a SoC

Hello,

So, the charge pump needs because we use a n-channel MOS pass device.
What's the reason of that we use n-channel MOS transistor as pass device?
Why don't we need an external capacitor? (Maybe the pass device gate source capacitance will guarantee the needed pole?)

Added after 4 hours 52 minutes:

Hello,

Does anybody have the article about the charge pump and nMOS pass element?:

O. Chevalerias, F. Rodes, K. Salmi, C. Scarabello: "4-V 5-mA low drop-out regulator using series pass N-channel MOSFET", Electron. Lett., vol. 35, pp. 1214-1215, July 1999


Thanks,

Re: What type of LDO structure for digital circuits in a SoC

We use an n-channel transistor as a pass device because we want to use source follower structure. If we use PMOS transistor as a pass devices, then we are using common source structure which has high output impedance without feedback. So at high-frequencies the output impedance of the regulator is high (because feedback is weak) so we need to use an external Cap to reduce the output impedance at high frequencies.
Here is your requested article:

how to simulation phase margin about LDO ?
someone tell me , OPA only act as "DC" buffer
don't care Phase margin , In gerneral ,
I sim phase margin is refere to
cmos circuit design layout & sim /baker

use large R + C in feedback . and calculate phase margin .