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  1. #1
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    verilog array

    for example,

    reg [7:0] mem [0:3];



    1. I want to initialize the every element in the mem = 0, how to do that?
    2. I want to initialize mem such that mem[0] = 2, mem[1] =4 , mem[2] = 1, mem[3] = 5. how to do that?

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    verilog initialize array

    write down all the values in a file and use
    $readmemh command


    3 members found this post helpful.

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    verilog array initialization

    $readmemh or $readmemb is not synthesizable.
    u can use it for simulation purpose.
    how to u realize in synthesis part?
    u must design a simple RAM for synthesis.

    Aravind



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    array verilog

    if you use register not memory,please use for loop
    to initialization!!



    •   Alt16th March 2006, 00:38

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    array in verilog

    I cant Understand JJWW110.
    can u give simple example.
    thanks



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    verilog memory array

    i guess what jjww said was

    Code:
    parameter MEM_SIZE = 1024
    reg [7:0] mem [0:MEM_SIZE -1]
    
    initial
    begin
    for (k = 0; k < MEM_SIZE - 1; k = k + 1)
    begin
        mem[k] = 0;
    end
    end



    •   Alt16th March 2006, 09:31

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    verilog memory initialization

    Is this correct? Looks like you actually treat mem as a single bit signal, not a bus signal.



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    verilog array initialize

    of course it is right, I often do as that



    •   Alt17th March 2006, 01:38

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    verilog array initial

    How about if I only want to initialize one of the bit of mem? For example, I want to initialize the bit 0 of all mem array to 0?



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    verilog initialize register

    Code:
    parameter MEM_SIZE = 1024
    reg [7:0] mem [0:MEM_SIZE -1]

    initial
    begin
    for (k = 0; k < MEM_SIZE ; k = k + 1)
    begin
    mem[k] = 8'h00;
    end
    end



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    verilog parameter array

    whether reg [7:0] mem[ 0:MEM_SIZE -1]

    the mem should be a ram file in the name of mem or
    verilog itself it take as ram memory?

    im having ram library of 512 X 8 (file name RAM512X8.v)
    how to write or involve it by using array structure like above ( ram [7:0] ---)



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    Re: verilog parameter array

    @weng

    You can intialize your bit 0 like this,
    parameter MEM_SIZE = 1024
    reg [7:0] mem [0:MEM_SIZE -1]

    initial
    begin
    for (k = 0; k < MEM_SIZE - 1; k = k + 1)
    begin
    mem[k][0] = 0;
    end
    end



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    Re: How to initialize an array structure in verilog?

    Actually $readmemh and $readmemb are synthesizable. Synthesis tools like Synplify Pro allow initial statements only for those functions. This is an example how I initialize the 2-D array mem with the file contents.txt:
    Code:
    reg [ 31:0] mem [0:4095];
    initial $readmemh("contents.txt", mem);
    In this case, the TXT file should only have hex characters and does not need to have the contents for all locations. For instance, something like this will initialize only the first location:
    Code:
    F3FA0B59



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    Re: How to initialize an array structure in verilog?

    i want to iniatialize array of reg [7:0]arr[15:0] using for loop ? anybody help me please..................



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    Re: How to initialize an array structure in verilog?

    Quote Originally Posted by jhunjhun View Post
    i want to iniatialize array of reg [7:0]arr[15:0] using for loop ? anybody help me please..................
    Hi jhunjhun, if you want to initialize the whole array with zeroes or ones, then you can use the approach presented by jjww110 (see above). If you have the initializing data in a file, then you use the tasks readmemh or readmemb (see above too). Could you share an example of the initial contents for a better picture of your problem?



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    Re: How to initialize an array structure in verilog?

    my problem is:
    reg [7:0]arr[15:0];
    reg [7:0]i;
    reg [1:0]state;
    always@(clk)
    begin
    case(state)
    2'b00: begin //arrary arr initialization//
    arr[i] <= i;
    if(i ==8'hFF)
    state = 2'b01;
    else
    begin
    i = i+1;
    state = 2'b00;
    end
    end

    2'b01: begin
    end
    endcase
    end
    Last edited by jhunjhun; 3rd June 2012 at 18:07. Reason: mistake



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    Re: How to initialize an array structure in verilog?

    jhunjhun, for a synthesizable memory initializer based on a state machine, I would only recommend you to initialize the addressing variable i.

    Code:
    input	clk, reset;
    
    // Declare states
    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
    // Declare max address (it could be less words)
    parameter MAXADDRESS = 8'bFF;
    parameter FILLINGVALUE = 16'b0000;
    
    reg [7:0] arr [15:0];
    reg [7:0] i;
    reg [1:0] state;
           
    always @ (posedge clk or posedge reset) begin
    	if (reset)
    		state <= S0;
    	else
    		case (state)
    		S0: begin
    			i <= 0;
    			state <= S1;
    		end
    		S1: begin
    			arr[i] <= FILLINGVALUE;
    			if (i == MAXADDRESS) begin
    				state <= S2;
    			end
    			else begin
    				i <= i + 1;
    				state <= S1;
    			end
    		end
    		S2: begin
    			// ...
    		end
    		endcase
    	end
    end
    If you want to fill it with the address, you will have to pay attention to the word length.



  18. #18
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    Re: How to initialize an array structure in verilog?

    thanks..........
    But if i want to fill data in array like as i incrementeted arr[i] <= i .

    - - - Updated - - -

    thanks..........
    But if i want to fill data in array like as i incrementeted arr[i] <= i .



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    Re: How to initialize an array structure in verilog?

    Quote Originally Posted by AlvaroJ View Post
    Actually $readmemh and $readmemb are synthesizable. Synthesis tools like Synplify Pro allow initial statements only for those functions. This is an example how I initialize the 2-D array mem with the file contents.txt:
    Code:
    reg [ 31:0] mem [0:4095];
    initial $readmemh("contents.txt", mem);
    In this case, the TXT file should only have hex characters and does not need to have the contents for all locations. For instance, something like this will initialize only the first location:
    Code:
    F3FA0B59

    k, for 1st locatioin, how to initialize all the memory locations.....



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    Re: How to initialize an array structure in verilog?

    Alvaro, I know it is more than one year later, and I'm posting only for the "future" generations :)
    I found this post when looking for a code for this same initialization, and maybe could be useful to let a very small contribution also:

    On the S1 state, I think it would be better to test if i is equal or greater than MAXADDRESS instead of equal to, in order to increase the tolerance to faults (if MAXADDRESS is not a power of two).

    Maybe something as:
    Code:
    ...
    		S1: begin
    			arr[i] <= FILLINGVALUE;
    			if (i >= MAXADDRESS) begin
    				state <= S2;
    			end
    			else begin
    				i <= i + 1;
    				state <= S1;
    			end
    		end 
    ...
    Quote Originally Posted by AlvaroJ View Post
    jhunjhun, for a synthesizable memory initializer based on a state machine, I would only recommend you to initialize the addressing variable i.

    Code:
    input	clk, reset;
    
    // Declare states
    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
    // Declare max address (it could be less words)
    parameter MAXADDRESS = 8'bFF;
    parameter FILLINGVALUE = 16'b0000;
    
    reg [7:0] arr [15:0];
    reg [7:0] i;
    reg [1:0] state;
           
    always @ (posedge clk or posedge reset) begin
    	if (reset)
    		state <= S0;
    	else
    		case (state)
    		S0: begin
    			i <= 0;
    			state <= S1;
    		end
    		S1: begin
    			arr[i] <= FILLINGVALUE;
    			if (i == MAXADDRESS) begin
    				state <= S2;
    			end
    			else begin
    				i <= i + 1;
    				state <= S1;
    			end
    		end
    		S2: begin
    			// ...
    		end
    		endcase
    	end
    end
    If you want to fill it with the address, you will have to pay attention to the word length.
    Thanks,
    Josias



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