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The propagation delay from high to low and vice versa

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sheraz.pervaiz

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Delays in digital gate

Why is the propopogation delay from high to low is different from low to high?

I can understand the reason why rise time is unequal to the fall time,but not about the difference in propogation delay
 

Re: Delays in digital gate

hi
lok this
 

Re: Delays in digital gate

thanx vicky,

But your information was of propogation delays in networks,I want to know about the delays in logic gates
 

Delays in digital gate

I dont understand what do you mean by delay propagation in high and low in logic gate?
 

Delays in digital gate

i tkink it must be because of different path of signal, in each case....
we know that the implementation of logic gates is done by some transistors and different logic levels are gained by varyig the bias level of these transistors....for example, high level on an output means the output transistor goes off. and the low level means that transistor goes in saturation state...
 

Delays in digital gate

In TTL logic device, which use bipolar transistor T(PHL) not equal to T(PLH).
because of switching charachteristic of BP transistror.
in BP transistor we have 4 timing regions.
turn on delay time, rise time, storage time, and fall time.
storage time compared to other timing is very long.
and this produce extra time needed to turn off transistor.
for over come to this problem shottky TTL borned.
I think in all other logic device similar phenomena cause this inequality.

Regards,
Davood.
 

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