Help with OrCad, Leonardo and Xilinx FPGA

Hi all,
I am new to the list and at my wits end. I am under pressure to complete a design targeting an old Xilinx xc4020. This is part of an upgrade to a legacy design. I am using a dedicated PC because it is the only one loaded with the software to compile these devices!
I am using OrCad 9.1 and Xilinx ISE 4.2. The synthesys tool is Leonardo. The design is done using VHDL. The problem comes when simulating, and compiling. I get errors similar to
: Error : [Load047] no port 'a_in6' found for entity 'RDBK_MUX2'
( this is one of my readback multiplexers) The error message is displayed when I compile or try to simulate. Strangely any individual block of VHDL, does not do this, only on the complete design.
I think the error is telling me that I do not have busses ( ie a_in like above) connected, but they are all there and defined in the code.
Anyone any ideas from the dim and distant past what this is all about?
Any help greatfully recieved.
Kind Regards
Jeff

Not all components are implemented. If you can use a higher version of orcad (10.3), you may have better luck because the lib's we redisigned to support 4.2.

Also orcad hates duplicate pins for xilinx devices. So if you took two block VHDL in your schematic you may have to change the port pins.

Can we see code please?

Some simulators do not properly support "direct instantiation", even if the synthesis tool does.

If you are using direct instantiation, you may need to redo the code to use the older and more cumbersome "component" declarations to define what port signals are available for each entity.

If there are no component declarations in the entire design, it may be an indication that the design was never simulated. The design might have been debugged by bringing out internal signals to spare pins for probing.

So instead of
use
and add to the list of declarations, a copy of your entity port declarations wrapped in component - end component, similar to the following: