Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Positive and negative edge trigger flip flops

Status
Not open for further replies.
S

surreyian

Member level 3
Joined
Feb 10, 2006
Messages
63
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,796
edge trigger fip flop

Hello,

everytime we talk about positive edge trigger and negative edge trigger flip flop.
how do we design a postive edge trigger flip flop?
how do we design it to trigger at the 5th positive edge trigger.
what determines the umber of clocks it triggers at?
 

Re: edge trigger fip flop

surreyian said:
Hello,

everytime we talk about positive edge trigger and negative edge trigger flip flop.
how do we design a postive edge trigger flip flop?
how do we design it to trigger at the 5th positive edge trigger.
what determines the umber of clocks it triggers at?
Click to expand...

hello,
what i know >>edge trigger FF can have many architectures , the most simple one
" for me" is using two oppositte latches "i.e. -ve latch then +ve latch >> +ve edge trig. , or +ve latch then -ve one >> -ve edge trigger" , about the # of edges u may use shift register (i.e. a series of registers with the edge u like "5 +ve in ur case" )
for the exact architectures "there r many" refer to any digital circuits book , i recommend RAbaey's >>dont remember its name .
bye.
 

Re: edge trigger fip flop

hello,

any recommendation on digital IC books, n where can i find them?
 

edge trigger fip flop

digital integrated circuits-a design perspective by rabaey is good.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top