How to suppress distortion of the SC sampling switches? Help

bottom plate sampling

Hi all,

To suppress the distortion of the sampling switches that needed to pass 500MHz bandwidth signal, some techniques has been done it before:

1) Increase the transistor size to reduce the on resistance, so that the distortion is suppressed. However, a big transistor also makes a bit parasitic capacitor. I tried this technique, the transmission gate transistors size turns out to be W/L=2700! to keep the THD as low as 0.1% at 500MHz. This size is ridiculous.

2) Bootstrapping technique, which keep the Vgs of the transistor constant when the switch turns on. Compare to technique 1), it only requires W/L=300 to keep the THD as low as 0.001%. However, this technique requires complicated layout. I been told that the guy who first pulish this technique spent one year on the layout!

3) Peoples saying that connect the source of the p-type transimission switches to the bulk(body) when the switch is on (on-resistance reduced), then connect it back to vdd when it is off (off-resistance increased). However, the distortion performance does not improved when I do the simulation in spice.

Does anyone have any advice regarding to this topic? Any suggestion would be greatly appreciated.

bottom-plate sampling

when you are doing 1st option, are you using bottom plate sampling?

bottom plate sampling thd switch size

Hi,

Thanks for the reply. I did use the bottom plate sampling and is in a fully differential architecture. However, when I simulate the THD in spice, the transimission switches are held on, and the bottom plate switches is tied to a common mode voltage. Since the switches are not switching, does it matter to the THD standpoint?

site:www.edaboard.com cmos switch

use cmos switch?

bottom plate sampling

Analogworld said:

Hi,

Thanks for the reply. I did use the bottom plate sampling and is in a fully differential architecture. However, when I simulate the THD in spice, the transimission switches are held on, and the bottom plate switches is tied to a common mode voltage. Since the switches are not switching, does it matter to the THD standpoint?

Click to expand...

confused by you. did you mean your switch turned off?

Re: How to suppress distortion of the SC sampling switches?

The switches are always turn on when simulating the THD. Therefore, I think the bottom plate sampling technique doesn't matter much in this case.

Re: How to suppress distortion of the SC sampling switches?

Analogworld said:

The switches are always turn on when simulating the THD. Therefore, I think the bottom plate sampling technique doesn't matter much in this case.

Click to expand...

I think bootstrap is ok. Layout is not a fatal problem as it is mature techs right now.
However distortion of SC sampling is not only contributed by the parasitic r, c during the switches "on" state, the MOS switches switching action may be more deadly and contribute more distortion.

Re: How to suppress distortion of the SC sampling switches?

Analogworld said:

The switches are always turn on when simulating the THD. Therefore, I think the bottom plate sampling technique doesn't matter much in this case.

Click to expand...

Thus, it worthwhile to remind that bigger mos-switch will incur more non-linear diffusion cap, which make the THD noticablely larger.

Re: How to suppress distortion of the SC sampling switches?

One way to reduce distortion is to ensure that the switches deal with constant VGS. There are a lot of circuits for this purpose. People also use Clock Voltage doublers for less distortion

Another way is to use bootstrapping. I do not think that the layout for bootstrapping is very complicated.

Re: How to suppress distortion of the SC sampling switches?

Thanks for all the advices!