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How to do cell mapping in RTL compiler

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rtl compiler virtual directory

Hi All,

My customer use Synopsys gtech gate level netlist verilog format
as hand-off format. (set target_library = gtech.db in DC)
But we use Cadence RTL compiler as synthesis tool.
How to compile Synopsys gtech gate netlist in RTL compiler to otimize
and map to technology library cells?
 

what does rtl compiler do ?

RTL compiler having GTech library incide /hdl_libraries
u can run synopsys netlist no problem will occur.
load_hdl RTL_PATH/*v
elab
techmap

run this commands
if u face any problem send the error message i will try to debug it
 

rtl compiler

aravind said:
RTL compiler having GTech library incide /hdl_libraries
u can run synopsys netlist no problem will occur.
load_hdl RTL_PATH/*v
elab
techmap

run this commands
if u face any problem send the error message i will try to debug it
Click to expand...

I don't find hdl_libraries directory and RTL compiler seems not to support thes commands your provided.
I only find gtech.alf.
 

synopsys gtech library mapping

Does RTL Compiler read synopsys technology file (.db) or just (.lib) ?
 

rtl compiler cadence [map-2] [synthesize]

hdl_libraries/
-- This is RC's virtual directory, not a directory under tool installation dir.

-- You can see this directory after you invoke rc, and type ls
rc> ls
rc:/> ls
./ designs/ hdl_libraries/ libraries/ messages/


-- Furthermore, you can browse the content of this virtual directory
rc:/> cd /hdl_libraries/

rc:/hdl_libraries> ls
 

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