Why do I get glitches when I simulate this program?

When I simulatiing the following prgrm,Why the glitches are coming in the output?..

module test(clk,a);
input clk;
output a;

reg a;

always @ ( clk )
begin
a=0;
a<=1;
$display(a);
end
endmodule

glitch

You should not see glitches in the text display. You should see a continuous stream of "0" values with no "1" values.

Each time a "clk" transition occurs, "a=0" immediately drives "a" low. "a<=1" schedules a go-high event to be executed after all active events complete. Since "$display(a)" is an active event, "a<=1" will update "a" after the "$display(a)". That's why you shouldn't see any "1" messages in the text output.

If you are looking at a waveform display in a GUI simulator such as ModelSim, it shows you a plot of the continuous value of "a" irregardless of $display statements. You will see "a" high most of the time, but glitching low briefly after every "clk" transition.

By the way, it's usually a bad idea to mix blocking and nonblocking assignments in the same "always" block.