Problem with using NMOS source follower to drive pass device

hello

i used simple one stage OTA to drive pass device, but the parasitic pole was too low, so i decided to use NMOS source follower.

its resistance is much lower, so the pole went to higher frequencies, but it's a double pole and i don't know why.

did i forget something?

regards

LDO+buffer

Interesting. In both cases you would have a pole from the OTA driving the gate, and also a pole from the output cap and load resistance. In the common-source configuration your OTA pole could have miller effect which may have split across your output pole. Where are the poles now? Could you estimate each of the intended poles based on your R-out and C?

Re: LDO+buffer

electronrancher said:

Interesting. In both cases you would have a pole from the OTA driving the gate, and also a pole from the output cap and load resistance. In the common-source configuration your OTA pole could have miller effect which may have split across your output pole. Where are the poles now? Could you estimate each of the intended poles based on your R-out and C?

Click to expand...

i use .PZ and it is exactly the same pole, of course this one form CL and RL also exists.

i have connected nmos bulk not to ground but source, to have Vbs=0 and double pole has appeared. if i connect bulk to gnd only single exists in this freq but i have problem with setting the operating point (i work on 1.3 vdd and 0.6-0.7 Vth)

the next strange thing is that this pole changes with load. for low current load it is in lower frequencies as the domain pole but with big load it goes to high freq.

I know it is normal for the first pole it changes with load current, but i'm not sure about opamp's pole. when we're talking about UGF do we mean low or high load conditions? For low condition UGF is smaller than for high one

one more thing. what buffer do you recommend for low voltage operation. the best one would give big current driving pass device input capacity during high load, and low current during low load condition to minimize power loss.

regards