XST synthesis error of an address sequence generator in Verilog

always @ (negedge init or negedge rst)
	begin
		if(rst==0)
		begin
			first = 14'b00_0000_0000_0000;
			last = 14'b00_0000_0000_0000;
			addr = 14'b00_0000_0000_0000;
			count = 13'b0_0000_0000_0000;
		end
      .
      .
      .
      end

ERROR:Xst:880 - seq.v line 47: Cannot mix blocking and non blocking assignments on signal <count>.
ERROR:Xst:880 - seq.v line 48: Cannot mix blocking and non blocking assignments on signal <addr>.
ERROR:Xst:899 - seq.v line 17: The logic for <first> does not match a known FF or Latch template.
ERROR:Xst:899 - seq.v line 18: The logic for <last> does not match a known FF or Latch template.
ERROR:Xst:899 - seq.v line 48: The logic for <addr> does not match a known FF or Latch template.
ERROR:Xst:899 - seq.v line 47: The logic for <count> does not match a known FF or Latch template.