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    Help me to estimate die size for chip in 0.13 process

    Hi,
    I am designing a chip, it's process is .13.
    I want to estimate die size for my chip.
    The chip gate count is 700,000, how much die size should i choose(no including IO)

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    nand die size

    Hi,
    you can ref. from this (TSMC 0.13micron - eight layer metal (8LM) copper wiring technologwith FSG (Fluoro-Silicate Glass))
    Code:
    Library  ------------------------------Raw Gate Density
    High density standard cell             ~256kgates/mm2
    High speed standard cell               ~230kgates/mm2
    Metal Programmable                     ~140kgates/mm2
    hope this help
    rgrds



    •   Alt19th January 2006, 07:40

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    reference book for die sizes

    Hi,
    Thanks very much
    Could you give TSMC 0.18 table?



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    die size

    TSMC 0.18 - 7LM
    Code:
    Library  ------------------------------Raw Gate Density 
    High density standard cell             ~180kgates/mm2 
    Metal Programmable                     ~109kgates/mm2
    Note: Above numbers are for estimation purpose only.



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    nand equivalent gate count 0.13 area

    I was using the die size calcualtion in different way. Finding out the module area from each macros (from the designs that has been completed already, we can statistically get the nandgate equivalent design area).

    eg.
    802.11a,b,g BB--> 500,000
    UART--> 9,000

    and then finding out nand equivalency of Scan Flops and non scan flops
    e.g. :
    1 Non-scan D-FF = 5.67 NAND2X1 gates
    1 Scan D-FF = 7 NAND2X1 gates

    Finally, from the technology file we can find the data about the area of each Nand gate.

    Total area= (each NAND gate area) * (no of equivalent Nand gates)


    Hi ami, can you tell me ... about the table... please suggest me, how to get this tables? whether from foundry or from third party or from our experts. Do you have the table for SMIC .35u , then I can test my way of calculation with this approximation.



    •   Alt20th January 2006, 10:35

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    artisan metro standard cell nand

    Hi,
    The die-size (and power,...) estimation may be obtained from TSMC/SMIC/.. techbook(ASIC technology data book - or anything they call it). The die-size depends much on the ASIC vendor's library/process-type... just contacts them and get these information.

    Your method of die-size calculation is correct if you get the NAND size in mm2.
    And the total area should be tot up from the Combinational area, Noncombinational area and Net Interconnect area - not the gate only.
    Rgrds



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    what is die size estimation

    Quote Originally Posted by ami
    Hi,
    The die-size (and power,...) estimation may be obtained from TSMC/SMIC/.. techbook(ASIC technology data book - or anything they call it). The die-size depends much on the ASIC vendor's library/process-type... just contacts them and get these information.

    Your method of die-size calculation is correct if you get the NAND size in mm2.
    And the total area should be tot up from the Combinational area, Noncombinational area and Net Interconnect area - not the gate only.
    Rgrds
    and area of hard macros also.



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    tsmc die area estimation note

    well the total area of the die umm very interesting because i would say the die area completely lyes on the hands on manufacturer.. can u attain tentative values of the die area dependin on the technology, scaling factors etc etc.

    has anyone designed and finally tapeout?

    please share your thoughts...

    with regards,
    arun



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    estimating die size

    Area is mainly down to the standard cell library you use, rather than foundry. For example, if you use Artisan Sage-X libaraies, die size will be the same for 0.13 for any fab (TSMC / Chartered / IBM / UMC). However, if you use Artisan Metro libraries, die size will be smaller, but same for each fab. If you want a smaller die, either change library of geometery.



    •   Alt21st January 2006, 21:23

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    mm2 die size

    what ami telling I accept.
    u have to sit with fab guys or ask datasheet for that particular technology about Die Sizing.
    now other way u cant calculate urslen.
    nandgate calculcation wont help u lot.
    it will give appr. value.
    u have consider lot more than that.
    power , temp, SI issues for density of cells.



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    die size 65nm + gate count

    aravind:
    what ami telling I accept.
    u have to sit with fab guys or ask datasheet for that particular technology about Die Sizing.
    now other way u cant calculate urslen.
    nandgate calculcation wont help u lot.
    it will give appr. value.
    u have consider lot more than that.
    power , temp, SI issues for density of cells.

    Well aravind, we are interested in finding the approx value only... the perfect value can be found at the later stage of PD, but while quotation, we have to tell the customer about an approximate size of the die. For this reason mainly, you need to do a die-size estimation. Even customers are appreciating companies those are giving this details before even starting the project. So without design (i.e. before getting the gate count) you have to give the quotation on the die-size. At this time you can't consider power, temp, SI issues for that chip. That's why I told the process of die-size estimation is also depends on the previously achieved data (and of course on the details from fab and the depth of experience).

    1. Find out major design blocks (bus architecture, functional IP blocks like 802.11.. etc)
    2. Get from your previous project database the module area of those.
    3. From the fab guys get the NAND size, and get the details of the scan and non scan flops.
    (of course other things has to be considered/assumed like scan flops mostly used, clk buffers mostly used, ScanEnable HFN percentage, Async Reset HFN percentage, Scan Chain Hold Fix percentage, Functional path Hold Fix percentage etc.)
    4. With these details, consider both combinational and non-combinational area (as ami said) [but the net interconnect area can not be incorporated in the estimation at these much early stage,.... to some extend it is covered as we took the module area from previous projects]

    and remember aravind, there are some companies those are using this method... so u can't say that I can't calculate the die-size with this method. People are using this method and that's why I am providing the information on this.

    and yes ami, the size of the NAND should be in mm2



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    nand diesize

    Hi,
    i totally agreed with usrlen description and if u want to calculate mathematically then go through ASIC text book by M. Smith, Chapter no.15 and he has explained very clearly about "Die Size".

    Prashant



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