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A question about process corner.

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holddreams

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process corner

I designed a folded-cascode opamp, and ran the simulation in tt_corner.
One of the MOS Ids=13uA, but when used ff_corner(other parameters not changed,only replace tt_corner by ff_corner), then Ids changed to 29uA, so large!
And when using ss_corner, this MOS cutoff!

How should I do?

Thanks.
 

Thats right ! You need to make your design more robust against process variation. A good voltage bias generator may help you in this case. How are you biasing your cascodes? A good bias can help track the process variation.

Good luck
 

I guess ,it may be because of the process model.
I did a test,just use a NMOS transistor ,whose source and bulk were connected to ground, and gave the gate a vin=3.3v, v(drain)=3.3v, then run .op,
and in the .lis file ,the Id change about 15% about tt_corner and ff_corner.
But if when vin=1.1v, v(drain)=3.3v, then the Id changed about 100% about tt_corner and ff_corner.
 

holddreams said:
I guess ,it may be because of the process model.
I did a test,just use a NMOS transistor ,whose source and bulk were connected to ground, and gave the gate a vin=3.3v, v(drain)=3.3v, then run .op,
and in the .lis file ,the Id change about 15% about tt_corner and ff_corner.
But if when vin=1.1v, v(drain)=3.3v, then the Id changed about 100% about tt_corner and ff_corner.
Click to expand...

what do you mean "because of the process model"?
Let's assume vth=1v(tt) vth=0.9v(ff) then
when vin=1.1v Vgs-Vth=0.1(tt) 0.2(ff);
but when vin=3.3v Vgs-Vth=2.3(tt) 2.2(ff);
so you can see why when vin is low the change ratio is large.
 

Please use ideal current source for check your biasing.
 

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