shell_inspector
Newbie level 2
xc9572 schematic
Hello,
I am working with a XC9572-pc44 CPLD using the free Webpack ISE7.1.1 For some unconown reason the simply implemented 8 bit binary counter ("hello world") won't do it's thing. Instead of having each bit deviding clock's frequency by 2, the frequency of each bit is clock/2. In addition the bits are jiggling in phase like:: 10101010010101011010101...
The clock is slow, about 1kHz, the Clear and CLk look fine on the Scope. Here's the source which is straight from the book. I suspect the ISE7.1.1 is buggy.
========
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port (
CLEAR: in std_logic;
Q5: out std_logic_vector(7 downto 0);
CLK : in std_logic);
end counter;
architecture Behavioral of counter is
signal Q5_IN : std_logic_vector(7 downto 0); -- Defines internal signals
begin
Q5 <= Q5_IN; -- Set output
process(CLEAR, CLK) begin
if CLEAR='1' then -- Clear counter ?
Q5_IN <= "00000000"; -- Yes. Clear counter
elsif CLK='1' and CLK'event then -- Clock rising edge ?
if Q5_IN=128 then -- Yes. Count = 4 ?
Q5_IN <= "00000000"; -- Yes. Clear counter
else -- No
Q5_IN <= Q5_IN + '1'; -- Count-up
end if;
end if;
end process;
end Behavioral;
Hello,
I am working with a XC9572-pc44 CPLD using the free Webpack ISE7.1.1 For some unconown reason the simply implemented 8 bit binary counter ("hello world") won't do it's thing. Instead of having each bit deviding clock's frequency by 2, the frequency of each bit is clock/2. In addition the bits are jiggling in phase like:: 10101010010101011010101...
The clock is slow, about 1kHz, the Clear and CLk look fine on the Scope. Here's the source which is straight from the book. I suspect the ISE7.1.1 is buggy.
========
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port (
CLEAR: in std_logic;
Q5: out std_logic_vector(7 downto 0);
CLK : in std_logic);
end counter;
architecture Behavioral of counter is
signal Q5_IN : std_logic_vector(7 downto 0); -- Defines internal signals
begin
Q5 <= Q5_IN; -- Set output
process(CLEAR, CLK) begin
if CLEAR='1' then -- Clear counter ?
Q5_IN <= "00000000"; -- Yes. Clear counter
elsif CLK='1' and CLK'event then -- Clock rising edge ?
if Q5_IN=128 then -- Yes. Count = 4 ?
Q5_IN <= "00000000"; -- Yes. Clear counter
else -- No
Q5_IN <= Q5_IN + '1'; -- Count-up
end if;
end if;
end process;
end Behavioral;
