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  1. #1
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    fifo timing

    I use SPARTANIII internal block ram as FIFO, but the timing can't satisfy my requirement, the detail is as below:
    I need 125Mhz speed, but the ram data out can only implement about 100Mhz, how can I improve the speed.

    thanks, ackqin



    Timing constraint: TS_lclk = PERIOD TIMEGRP "lclk" 7.5 ns HIGH 50%;

    20913 items analyzed, 63 timing errors detected. (63 setup errors, 0 hold errors)
    Minimum period is 9.989ns.
    --------------------------------------------------------------------------------
    Slack: -2.489ns (requirement - (data path - clock path skew + uncertainty))
    Source: xmt_scheduler/addq_fifo/addq_fifo/B8.B (RAM)
    Destination: xmt_scheduler/addq_fifo/addq_dout_6 (FF)
    Requirement: 7.500ns
    Data Path Delay: 9.970ns (Levels of Logic = 3)
    Clock Path Skew: -0.019ns
    Source Clock: lclk_BUFGP rising at 0.000ns
    Destination Clock: lclk_BUFGP rising at 7.500ns
    Clock Uncertainty: 0.000ns
    Timing Improvement Wizard
    Data Path: xmt_scheduler/addq_fifo/addq_fifo/B8.B to xmt_scheduler/addq_fifo/addq_dout_6
    Delay type Delay(ns) Logical Resource(s)
    ---------------------------- -------------------
    Tbcko 2.394 xmt_scheduler/addq_fifo/addq_fifo/B8.B
    net (fanout=1) 3.044 xmt_scheduler/addq_fifo/addq_fifo/N942
    Tif5 0.796 xmt_scheduler/addq_fifo/addq_fifo/BU197
    xmt_scheduler/addq_fifo/addq_fifo/BU203
    net (fanout=1) 0.000 xmt_scheduler/addq_fifo/addq_fifo/N8868
    Tif6y 0.342 xmt_scheduler/addq_fifo/addq_fifo/BU216
    net (fanout=1) 0.358 xmt_scheduler/addq_fifo/addq_dout_<6>
    Tilo 0.551 xmt_scheduler/addq_fifo/_n0025<6>9
    net (fanout=1) 1.459 CHOICE1368
    Tsrck 1.026 xmt_scheduler/addq_fifo/addq_dout_6
    ---------------------------- ---------------------------
    Total 9.970ns (5.109ns logic, 4.861ns route)
    (51.2% logic, 48.8% route)

    •   Alt5th January 2006, 02:27

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  2. #2
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    fifo timing

    If you tell us exactly which chip you are using, and show us your design, maybe someone can help you better.

    "Data Path Delay: 9.970ns (Levels of Logic = 3)" -- That seems slow for only three levels of logic. Maybe your layout has long sprawling routes.



    •   Alt5th January 2006, 05:03

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  3. #3
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    how can I improve FIFO timing?

    echo47, thanks.
    I use xc3s400 -4, I only use this fifo in FPGA, all the signal is in the fpga.
    This fifo saves my data, and I will read out when I need. so I want to know, but the data out speed of fifo can't satisfy my 125Mhz requirement, so I want to know is there any way can make the data quicker out from fifo.



    •   Alt5th January 2006, 06:05

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  4. #4
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    how can I improve FIFO timing?

    That FPGA can easily go 125 MHz, so there's probably an inefficiency somewhere in the FIFO design. That's all I can say without seeing the design.

    If you have coregen, try using it to make the FIFO. You may have better luck.



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