How to improve the area power and delay of standard cells?

why we keep height fixed in standard cell

hi....................
can any body tell me that how can i improve the area power and delay of standard cell like flip flops and latches. and what iss the responsebilities of standard cell library development engineer.
plz help me

why height is fixed in standard cell

Well, in a Standard-cell based design, the dimensions of the standard cells are fixed. For example, a standard cell inverter will have a cell width of 12λ and a cell height of 20λ. You cannot exceed these rules. These are designed in such as way to reduce the area and also the delay. Since the area is minimized, the delay also gets minimized due to the lesser metal used for interconnects. So, the area and delay problems are taken care of.

For a particular technology, the power consumption will be known. As you know, in CMOS ckts, the main power consumption is in the Dynamic power consumption. But you also have to take into account the leakage power and other factors.

In general, the standard cell based design is used to reduce the area of designs and also for design reuse. It makes the physical design part of chip design easier and also reduced the time-to-market. Moreover, since the cell libraries are provided by the fabrication houses, when a design is done using these libraries, it takes them lesser time to implement on Silicon and also all the parameters are already known.

Re: Layout of standard Cell

Thnak you very much for the reply....
what i understand is that we can minimize delay by minimizing area ,and power consumption by reducecing supply voltage and load capacitance. But the most important optimization is still not done ..........timing plz tell me how can i control setup time , hold time, rise time ,fall time in order to meet particular specification in case of latches and fipflops.

thakyou
Regards
sahil

Layout of standard Cell

setup time , hold time are meaningless for normal standard cell,
what you must consider are propagation delay, output rise time and fall time, you can adjust w/l of transistors, circuit structure and reduce internal cap to optimize them.
you can reference Digital Integrated Circuits A
Design Perspective(Senond Edition)

Re: Layout of standard Cell

Hi All.........
Thankyou very much for the reply........?
I have to develope a standard cell library and i dont hv much experience so i need help from you people.
suppose i hv to design a Layout of flip-flop cell so what are the things which i 'll hv to keep in mind and what r the special considerations.

expecting help from ur side

regards
sahil

Layout of standard Cell

Always keep the cell characterization as the last resort.

The library vendor can always do better than you, even though the parameter are rather conservative in case of the process violation and the yield.

beside, these figurs are obtained from more than the SPICE tools, but the realy chip test result.

Re: Layout of standard Cell

Always keep the cell characterization as the last resort.

The library vendor can always do better than you, even though the parameter are rather conservative in case of the process violation and the yield.

Click to expand...

Basically yes, but not always. I have an example:
Standard I/O for crystal oscillator.
Parameter : Power(uW/MHz).
I am sure the most vendors (at least TSMC) estimate this parameter as follows: apply square waveform with standard falling and rising edge to the input and sweep frequency. After that interpolate the Power - frequency relationship by linear function.
But the fact is that the input signal in real application is almost sine wave because of filtering by high Q quartz resonator. So through current will be much higher than in case of square wave.

I had to redesign this Standard Cell by myself because power was very critical issue for our device.

Re: Layout of standard Cell

vlsi_whiz said:

Well, in a Standard-cell based design, the dimensions of the standard cells are fixed. For example, a standard cell inverter will have a cell width of 12λ and a cell height of 20λ. You cannot exceed these rules.

Click to expand...

Agreed with all the things VLSI_WHIZ says, but the width of standard cell is not fixed. In a Library you have a lot of standard cells that have different width...
May be vlsi_whiz wants to say that the width is fixed for a single cell (doesn't change for pull-up and pull-down).... And globally all the cells must have same height....

Re: Layout of standard Cell

As far I know, the cell height of std.cell Lib is fixed & the cell width can vary..

In Lib itself there are lots of varieties.
Eg:
High Speed
High Density
High perfomance like that.

Re: Layout of standard Cell

is your question only on the circuit design or do you wnat to know the physical esign aspect too....