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set-up violations will degrade your chip performance such as highest working frequency, but no impact on the function.
hold violation will deadly hurt your chip's function.
So hold violation must be overcomed.
but set-up violation can be overcomed by decreasing the working frequency.
Fix them can be processed in the synthesis and layout phase.
What happens to the design if hold time violations occur,
Cud u explain " hold violation will deadly hurt your chip's function".
What actually happens to the chips functionality when hold violations occur.
if possible cud any one explain indetail
Do u mean to say when hold violations occur for eg on a register/ff it goes into metastable state. but meta stability can be overcome by using some hardend ffs
If your input signal to the ff is asynchronous to the clk, i think timing violation is unavoidable, but you can synchronize your signal before input it to ff.
setup vio is related to the clock period, and hold time violation have nothing to do with the clock period. So increase the clock period can help setup violation, but never hold violation. It means the chip have setup violation is inferior but the chip have hold time violation is wastrel. (exaggeratly)
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