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The effect of clock values when inserting clock tree in SE

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beckchm

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about CTGen

When inserting the clock tree in SE,there are some values about the clock ,for example max skew , transition time.
who does know the effect of the values?
 

Re: about CTGen

Max skew means the difference between the clock arrive the cloest and furthest register.
transition time: decided by the drive capacitance of the cell.
Both them can impact the performance of the chip such as the highest working frequency
 

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