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In a single SRAM memory cell, there are two NAND or NOR gates. You simply take the number of Transistors in a single NAND or NOR gate and multiply by 2.
I am not so sure with teh DRAM memory. But as far as I remember, the columns of a DRAM memory are interconnected together.(I am not sure wih this maybe the rows). Thats why you noticed its pretty fast to erase the contents of the memory because either the rows or columns are interconnected. the number of MOSFET in a DRAM memory is not based on per cell basis but on per number of COLUMNs (in case the columns are interconnected) or number of ROWS ( in case the ROWS are interconnected). The number of Columns denotes how wide is your memory word and the number of rows denotes to the memroy capacity. The MOSFETs are used to refresh the capacitors in a column.
Like I said i not so sure with the DRAM but I think if I remembered it correctly, thats the way how to count the MOSFETs in the DRAM
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