What type of capacitor should I use for generating POR delay

pordesign

Hi all,

What type capacitor do you use for generate POR deassertion delay, MOS or MIM?
If use NMOS cap (just 10umX10um M=50 NMOS device), I found it can't be charged to VDD and just around 500mV by simulation. So can't reach the Vth of comparator and function error.
Why the NMOS cap has such characteristic and how to solve this problem?

Thanks and Regards
Analog_starter

delay time por circuit

I will suggest to use integral circuirt for this application, or your POR circuit, but directly use of capacitors is a not very good idea, many time i had a problems exactly with POR or Reset schem with capacitor only . Maxim - Dalas have a good chip, TI too.

site:www.edaboard.com por circuit

Hi Tohu,

Thank you for your reply.
Actually I am designing the POR integrated circuirt. And the capacitor
is used for on-chip.

Analog_starter

Re: About POR design

generate POR deassertion delay

Click to expand...

Usually, I will use small delay (e.g. 0.5us~1us) cell, and then cascade many unit cells to form a large delay.

Re: About POR design

Hi Btrend,

Thank you for your reply.
Could you show me the detail structure of the small delay cell?
And how to cascade them to a large delay?
Why not use NMOS or MIM capacitor? Any shortcoming?

Thanks & Regards
Analog_starter

Re: About POR design

1. delay cell is simply composed of 2 inverters and one MOS cap between them, one of the two inverter is weak type, and the other is medium type. u had to simulate it against VCC, tempearture, corner to find a optimum W/L v.s. delay time.
2. in talking about the above , I assume that u had already a POR signal , and all u want to do is delay it until the VCC is ready. but from ur description, it seem that u will compare the POR with some reference ?
3. if possible, post ur schematic or idea.

Re: About POR design

Hi Btrend,

Sure! Actually my structure followed ambreesh's post. I have no
POR signal and just use the charge capacitor delay to comparator to generate
it.


21 Feb 2005 10:37 Re: Power on reset

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I shall tell what i have used.
1. A resistor devider. One of the resistors must be adjustable.
2. A BGR
3. A comparator with internal hystersis. With one input frpm BGR and other from resistor devider.
4. Assume BGR is negative input and resistor devider is positive input. When supply hits its positive threshold, comparator output goes high.
5. this output goes to a switch that connects a current source to a capacitor.
6. Capacitor is shorted to ground by a switch which is controlled by the first comparator output.
7. Charging of the capacitor determines the delay time.
8. Feed the output of the capacitor and BGR to anaother comparator. Once the cap charges beyond BGR voltage the POR is deasserted.