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[VHDL] initialization sequence

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OvErFlO

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hd44780 vhdl

What's the best method in VHDL to create a inizialization sequence ?

I have to create this sequence :


Code: 
reset button

15 msec  wait
 5  msec create a trigger _--_  to sample init data
 5  msec create a trigger _--_  to sample init data
120 usec create a trigger _--_ to sample init data

Loop
    wait until event occurent
    120 usec create a trigger _--_ to acquire data
end Loop

can anybody help me ?
Can I use a FSM or I can write in another way ?

thanks
 

vhdl initialize std_logic_vector

You can do something like this.....
Sample the data whenever there is an event on trigger signal.
Code: 
signal reset : std_logic := '1';
signal trigger : std_logic := '0';
signal event : std_logic := '0';

process
begin  -- process
  -- reset button
  reset <= '0';
-- 15 msec  wait
  wait for 15 ms;
--  5  msec create a trigger _--_  to sample init data
  wait for 5 ms;
  trigger <= not trigger;
--  5  msec create a trigger _--_  to sample init data
  wait for 5 ms;
  trigger <= not trigger;
-- 120 usec create a trigger _--_ to sample init data
  wait for 120 us;
  trigger <= not trigger;
-- Loop
--     wait until event occurent
--     120 usec create a trigger _--_ to acquire data
-- end Loop 
  while ('1') loop
    wait until event'event;
    wait for 120 us;
    trigger <= not trigger;
  end loop;
end process;
 

vhdl initialize variable

No testbench, but a vhdl synthesizable code...
 

vhdl initialization

You could use a FSM

First state: reset state, stay in this state as long as reset button is pushed

Second state: wait state, stay in this state for 15 ms, you can do this with a counter

Third state: again with a counter befor going to the next state

...

My advice to you is to not use a counter in each state, but to create an internal "clock" signal, you could use real internal clock signals, i don't know how far you want to go in this.

It is not wise to use a counter for each state. this will consume needless resources. maybe you can share counters for several states.

kind regards, Jef
 

vhdl initialize

Can you write a bit of VHDL ? I undestand what I do, but I can't understand how write code to do this...

thanks

Added after 1 hours 20 minutes:

I have write a code, can anybody,if it's possible, optimize this :

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lcd_driver_v2 is
    Port ( clk : in std_logic;
    		 rst : in std_logic;
           D7_D0_in : in std_logic_vector (7 downto 0);
		 empty : in std_logic;
		 D7_D0_out : out std_logic_vector(7 downto 0);
           RS : out std_logic;
           EN : out std_logic;
		 conteggio: out std_logic_vector (15 downto 0));
end lcd_driver_v2;

architecture lcd_driver_arch of lcd_driver_v2 is

type tipo_stato is (stato0,stato1,stato2,stato3,stato4,stato5,stato6,stato7,stato8,stato9);
signal stato : std_logic_vector(3 downto 0);

type rom_array is array (0 to 4) of std_logic_vector (7 downto 0);
	constant rom: rom_array := ("00000000",
						   "00011110",
						   "00011110",
						   "00011110",
						   "00111000");
signal clk_200u : std_logic;

begin

	
	
	U1_clk_div : process (clk) 
	variable v_count_clk : INTEGER RANGE 0 to 10001;
	begin
		if (rising_edge(clk)) then
			v_count_clk := v_count_clk + 1;
			if (v_count_clk > 10000) then -- if (count = 20001) then
				clk_200u <= NOT clk_200u;
				v_count_clk := 0;	
			end if;		
		end if;
	end process;

	
	U2_state_machine : process (stato, clk_200u, rst)
	variable v_count : INTEGER;
	begin
		if (rst = '1') then
			D7_D0_out <= "00000000";
			RS <= '0';
			EN <= '1';
			stato <= "0000";
			v_count := 0;
		elsif (rising_edge(clk_200u)) then			
			v_count := v_count + 1;
			case stato is 
				when "0000" =>
					if (v_count = 76) then
						D7_D0_out <= "00000000";
						RS <= '0';
						EN <= '1';
						stato <= "0001";
						v_count := 0;
					else
					   	D7_D0_out <= "00000000";
						RS <= '0';
						EN <= '1';
						stato <= "0000";
					end if;
				when "0001" =>
				
					if (v_count = 26) then
						D7_D0_out <= "00001111";
						RS <= '0';
						EN <= '0';					
						stato <= "0010";
						v_count := 0;
					else
						D7_D0_out <= "00001111";
						RS <= '0';
						EN <= '1';	
						stato <= "0001";								
					end if;
				when "0010" =>
				
					if (v_count = 2) then
						D7_D0_out <= "00000001";
						RS <= '0';
						EN <= '0';					
						stato <= "0011";
						v_count := 0;
					else 
						D7_D0_out <= "00000001";
						RS <= '0';
						EN <= '1';		
						stato <= "0010";		
					end if;
				when "0011" =>
				
					if (v_count = 2) then
						D7_D0_out <= "00111100";
						RS <= '0';
						EN <= '0';					
						stato <= "0100";
						v_count := 0;
					else
						D7_D0_out <= "00111100";
						RS <= '0';
						EN <= '1';		
						stato <= "0011";		
					end if;
				when "0100" =>
				
					if (v_count = 2) then
						D7_D0_out <= "00011100";
						RS <= '0';
						EN <= '0';					
						stato <= "0101";
						v_count := 0;
					else
						D7_D0_out <= "00011100";
						RS <= '0';
						EN <= '1';		
						stato <= "0100";		
					end if;
				when "0101" =>
				
					if (v_count = 2) then
						D7_D0_out <= "00001010";
						RS <= '0';
						EN <= '0';					
						stato <= "0110";
						v_count := 0;
					else
						D7_D0_out <= "00001010";
						RS <= '0';
						EN <= '1';		
						stato <= "0101";		
					end if;
				when "0110" =>
				
					if (v_count = 2) then
						D7_D0_out <= "00000001";
						RS <= '0';
						EN <= '0';					
						stato <= "0111";
						v_count := 0;
					else
						D7_D0_out <= "00000001";
						RS <= '0';
						EN <= '1';		
						stato <= "0110";		
					end if;
				when "0111" =>
								
					if (v_count = 2) then
						D7_D0_out <= "00000111";
						RS <= '0';
						EN <= '0';					
						stato <= "1000";
						v_count := 0;
					else
						D7_D0_out <= "00000111";
						RS <= '0';
						EN <= '1';
						stato <= "0111";
					end if;
				when "1000" =>
								
					if (v_count = 2) then
						D7_D0_out <= "00001110";
						RS <= '0';
						EN <= '0';					
						stato <= "1001";
						v_count := 0;
					else
						D7_D0_out <= "00001110";
						RS <= '0';
						EN <= '1';
						stato <= "1000";
					end if;
				when "1001" =>							
					if (v_count = 2) then						
						if ( empty = '0' ) then
							D7_D0_out <= D7_D0_in;
							RS <= '1';
							EN <= '0';					
							stato <= "1001";
							v_count := 0;
						else
							D7_D0_out <= D7_D0_in;
							RS <= '1';
							EN <= '1';					
							stato <= "1001";
						end if;							
					else
						D7_D0_out <= D7_D0_in;
						RS <= '1';
						EN <= '1';
						stato <= "1001";
					end if;	
				when OTHERS =>
					stato <= "0000";
			end case;		
		end if;	
		conteggio <= CONV_STD_LOGIC_VECTOR(v_count,16);		
	end process;				    


	

end lcd_driver_arch;
 

initialize in vhdl

I,m not going to write the code for you, but if you are trying to get a hitachi HD44780 controller to work have a look at my site, just dig through my code.

It's one way to do it.

**broken link removed**

kind regards, Jef
 

signal initialization vhdl

your site doesn't works... :cry:
 

how to initialize lcd in vhdl

yes, it does, link is correct, i just clicked it and it works
 

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