Does Thold affect clock period at all ?

Hi,

I am learning timing analysis, and came to this question. would appreciate if you can confirm my thought/learning. thanks.

since

Thold <= Tmindelay + Tclktoq,

I concluded that Thold requirement does not influence operating frequency at all. Is this correct ?

I do think clock skew can induce hold violation, because data might be changing too fast relative to late clock edge induced by skew. How about skew that actually hurts the Tsetup(the clock edge that comes too early due to skew) ? I'd suppose it would help hold requirement, even though it reduces setup margin. Am I on track?

yes, Thold doesn't affect clock period normally.
but sometimes it affects the slowest frequency you can run.

yeewang said:

but sometimes it affects the slowest frequency you can run.

Click to expand...

Can you give me a example?

thanks in advance!

to avoid hold violation
Th > Tcmin + Tcq

if the FF have low Th but high Tcq than Th, then to avoid violation, we should add some combinational delay, using buffers or inverters. that combinational part will have some Tcmax ( max comb delay). that will affect the maximum operating freequency of the circuit. ie Th affects the max clk freq.

if anything wrong, correct me.

. _____ ____
-----|D Q|-----comb logic----|D Q|----
-----|C | ---|C |
| |____| | |_ __|
|---------------delay buf--- |

try caculate the timing for this simplest circuit.

Just given Tsetup, Thold, Tclk2q, Tdelay and Tcomb different random numbers.

If you can do this, you would be able to caculate anything else.

God, the display ....

ok, let's try this.

The circuit is like the following.

always @(posedge clk)
q1 <= d1;

comb u_comb(.in(q1), .out(comb_out));

delay u_delay(.in(clk), .out(delay_clk));

always @(posedge delayed_clk)
q2 <= comb_out;

kslim said:

Hi,

I am learning timing analysis, and came to this question. would appreciate if you can confirm my thought/learning. thanks.

since

Thold <= Tmindelay + Tclktoq,

I concluded that Thold requirement does not influence operating frequency at all. Is this correct ?

I do think clock skew can induce hold violation, because data might be changing too fast relative to late clock edge induced by skew. How about skew that actually hurts the Tsetup(the clock edge that comes too early due to skew) ? I'd suppose it would help hold requirement, even though it reduces setup margin. Am I on track?

Click to expand...

Strictly speaking, the frequency or the clock period(better the valid triggering level width, for example the clock high-level width) cannot be too small. It must be larger than the Thold otherwise the Q-level shall be determined by the time width of the clock's valid level. For the same reason, during the invalid clock level, the Flipflop stores the input data value which will also take some time; therefore the invaid(low) level width shall be larger than the Tsetup. In all, the Tclock>Tsetup+Thold. For better comprehension, you shall analyze the signal transition mechansim of the D-FlipFlop as an example.


Thosmon