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how to design a decimation filter?

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yiyin

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Hi, I meet some problem in designing a decimation filter for a sigma-delta ADC
I don't have much experience in digital filter design, so I am quite confused when
look into the principle of the decimation filter.
Suppose we have a bit stream, the frequency is Fs and OSR is M
the averaging of M bits single can only produce an output of log2(M) bits resolution.
I konw there is a LPF, which is a sinc filter in many cases, after the decimator, but the output of the LPF should also be a one-bit output. So I am wondering how we can get this kind of high-resolution output?
Thank you very much to look into this issue :)
 

You'll find a lot of information on decimation filter design in the yellow book by Prof. Temes.
One point I'm not sure to understand.... You said the LPF output must be 1 bit. Is it your design requirement?
Honneslty if that's the case it's difficult. Indeed decimation filters reduce the frequency but increase the number of bit to keep the resolution.
Here are some ideas:
- Decimation Filter + Digital DSM -> you can put back to 1bit resolution but need a little OSR. Maybe less than the initial one.
- 1bit LPF: I've seen some article recently in a conf. (sorry I don't have it) about 1bit digital signal processing
Good luck
 

Please read Altera application notes. They expalin. how to design it and how to architect it.
 

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