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help me in converting following matlab code to verilog

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neha_agarwal2k3

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I have got to convert the following matlab code to verilog code as a part of my project work ..Some one plz help me....

/*This function takes in 500X500matrix as parameter and checks for each of the element for zero .If a non zero value is present ,it maintains a count of number of such values as well as maintains a summation of the position(row &column Value )
of all such elements*/

function npos=nposn(c)
c=double(c);
c=c-1;
countx=0;
county=0;
countpos=0;
for(i=1:500)
for(j=1:500)
if(c(i,j)~=0)
countx=countx+i-1;
county=county+j-1;
countpos=countpos+1;
end
end
end
posx=countx/countpos;
posy=county/countpos;
npos=[posx posy];
 

I hope you don't need to synthesize that! Floating point, large array, division ...

Why change c to double? What was it before?

Why the c=c-1?

Here's a more-or-less straight translation (untested). However, Verilog module ports can't be reals or arrays, so if you want a stand-alone module, you'll need to find another way to do I/O, maybe by using $realtobits() and $bitstoreal().
Code: 
module nposn;
  real c[1:500][1:500], posx, posy;
  integer i, j, countx, county, countpos;

  initial begin
    for (i=1; i<=500; i=i+1)
      for (j=1; j<=500; j=j+1)
        c[i][j] = c[i][j] - 1;
    countx = 0;
    county = 0;
    countpos = 0;
    for (i=1; i<=500; i=i+1) begin
      for (j=1; j<=500; j=j+1) begin
        if (c[i][j] != 0) begin
          countx = countx + i - 1;
          county = county + j - 1;
          countpos = countpos + 1;
        end
      end
    end
    posx = countx / countpos;
    posy = county / countpos;
  end
endmodule
 

I need to synthesize this model and view the netlist...so i have to definitely get the 500X500 matrix as input and should have output ports
Also the code is not getting compiled ...Im getting errors as unsupported Real variable.
The input matrix c has its values in uint8 format...For precision I have converted it to double ...so the step :(c=double(c)) is not compulsory

plz help me
 

There's a huge difference between Verilog and synthesizeable Verilog. There's no chance in the world that my example can be synthesized.

Ok, you don't need floating point data, so integers are fine everwhere except maybe those final divisions. Division and floating-point (real) are extremely painful in synthesis, so most tools don't support them. Try to eliminate them somehow.

You *must* find a different way of representing your input data. You cannot pass an array to a Verilog module. Where is this array stored? It's too big to store inside most FPGAs. External RAM? Arriving in real-time through a small input port? The whole architecture will depend on how you do this.
 

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