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Fault coverage in BIST circuit

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I'm designing a BIST circuit for memory application using Verilog codes. Once I've got my design ready, how can I evaluate the fault coverage in my design - BIST? What's the normal practice?
 

Unlike random logic, we need to consider many more fault models for memories. Stuck-at fault model alone is not sufficient, since the density of SRAMs can cause transition, open, coupling, and many other different faults.
When you need to design a BIST circuitry, you would first select a known BIST algorithm to implement, normally some kind of March algorithm. The effectiveness of these well know BIST algorithms is documented in various papers. A good reference is Van de Goor's book "Testing Semiconductor Memories".
Here is a link to his paper on the effectiveness of different BIST algorithms in testing DRAMs. You can look at its references to read about testing SRAMs.

**broken link removed**
 

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